[U-Boot] [PATCH 1/3] powerpc/p5040: enable NAND boot support

[Scott Wood]

On 01/17/2013 08:45:36 PM, Xie Shaohui-B21989 wrote:
> > -----Original Message-----
> > From: Wood Scott-B07421
> > Sent: Thursday, January 17, 2013 4:29 AM
> > To: Xie Shaohui-B21989
> > Cc: u-boot at lists.denx.de
> > Subject: Re: [U-Boot] [PATCH 1/3] powerpc/p5040: enable NAND boot  
> support
> >
> > On 01/15/2013 08:39:38 PM, Shaohui Xie wrote:
> > > Signed-off-by: Shaohui Xie <Shaohui.Xie at freescale.com>
> > > ---
> > >  boards.cfg |    1 +
> > >  1 files changed, 1 insertions(+), 0 deletions(-)
> > >
> > > diff --git a/boards.cfg b/boards.cfg
> > > index e4b0d44..8cf4936 100644
> > > --- a/boards.cfg
> > > +++ b/boards.cfg
> > > @@ -855,6 +855,7 @@ P5020DS_SECURE_BOOT          powerpc
> > > mpc85xx     corenet_ds          freesca
> > >  P5020DS_SPIFLASH	     powerpc     mpc85xx
> > > corenet_ds          freescale      -
> > > P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
> > >  P5020DS_SRIO_PCIE_BOOT          powerpc     mpc85xx
> > > corenet_ds          freescale      -
> > > P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
> > >  P5040DS                      powerpc     mpc85xx
> > > corenet_ds          freescale
> > > +P5040DS_NAND		     powerpc     mpc85xx
> > > corenet_ds          freescale      -
> > > P5040DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
> > >  BSC9131RDB_SPIFLASH          powerpc     mpc85xx
> > > bsc9131rdb          freescale      -
> > > BSC9131RDB:BSC9131RDB,SPIFLASH
> > >  stxgp3                       powerpc     mpc85xx
> > > stxgp3              stx
> > >  stxssa                       powerpc     mpc85xx
> > > stxssa              stx            -           stxssa
> >
> > This needs more explanation.  What sort of image am I supposed to  
> get
> > when I build "P5040DS_NAND"?  Where is the PBI?
> [S.H] there is already a readme for p3041/p5020/p4080  
> (doc/README.pblimage),
> With the PBL tool, we will get a ramboot image "u-boot.pbl".
> and also the PBI, it is shared by P3/P4/P5.

The question is how is the user to know that something called  
"pblimage" is relevant to booting from NAND on P5040?  Maybe a  
README.corenet_ds (or board/freescale/corenet_ds/README), that points  
to README.pblimage?

You don't even update strings like "P3041/P5020" in README.pblimage to  
include P5040. :-)
Why is P4080 excluded, BTW?  I realize that P4080DS doesn't have NAND,  
but the file talks about chips, not boards.

> > What is the long-term plan for fixing the problem of the  
> environment not
> > being available until after relocation?  With SPL we could use
> > CONFIG_NAND_ENV_DST (which has some issues, but they're fixable).
> [S.H] this will need export some NAND read APIs (like load ENV stuff  
> from CONFIG_NAND_ENV_DST),
> then they can be reused before relocation even not using SPL.
> Please suggest.

The full NAND subsystem will not work before relocation.  Your options  
are to either use SPL (note that you'll have no 4K limitation in this  
case, so you can do SPD DDR init), or make the SPL code available in  
non-SPL context somehow.  I think the former would be easier.

> > It would also be nice to include instructions for configuring the  
> board
> > to boot from NAND in a README
> [S.H] This exist in the above readme.

I only see hardware switch settings.  Is there no way to soft-boot into  
NAND (similar to using "pixis/qixis altbank" to boot into an alternate  
NOR bank)?  Our e500v2-based boards have been able to do this...

> (Freescale's user manuals often do not make
> > this clear, especially for soft configuration).  Also please  
> provide a
> > built-in command (or script in the default environment) to  
> soft-boot into
> > NAND (or if it already exists, please document it).
> [S.H] I was told that when doing ramboot, I should not assume the  
> board has a NOR flash,
> for ex. on customer's board, they may only have NAND. So I did not do  
> this.

I'm not asking you to assume that, just to provide some helpful  
instructions for people who happen to have both (in addition to the  
hardware switch instructions that are already there).  Actually, these  
instructions (both soft boot and hardware switches) are board-specific  
rather than SoC-specific and should go in a board README instead.  And  
once you know we're talking about a corenet_ds board, you know we have  
NOR.

-Scott