[U-Boot] [PATCH 8/9] mxs: Fix MMC reset to avoid write errors and timeout in iMX23

[Otavio Salvador]

On Mon, Jan 21, 2013 at 11:49 PM, Marek Vasut <marex at denx.de> wrote:
> Dear Otavio Salvador,
>
>> This does the same reset mask as done in v3.7 Linux kernel code; it
>> fixed the saveenv command in mx23evk.
>>
>> Signed-off-by: Otavio Salvador <otavio at ossystems.com.br>
>> ---
>>  drivers/mmc/mxsmmc.c | 16 +++++++++++-----
>>  1 file changed, 11 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c
>> index 618659e..0a3f0c4 100644
>> --- a/drivers/mmc/mxsmmc.c
>> +++ b/drivers/mmc/mxsmmc.c
>> @@ -354,11 +354,17 @@ static int mxsmmc_init(struct mmc *mmc)
>>       /* Reset SSP */
>>       mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
>>
>> -     /* 8 bits word length in MMC mode */
>> -     clrsetbits_le32(&ssp_regs->hw_ssp_ctrl1,
>> -             SSP_CTRL1_SSP_MODE_MASK | SSP_CTRL1_WORD_LENGTH_MASK |
>> -             SSP_CTRL1_DMA_ENABLE,
>> -             SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS);
>> +     /* Reset MMC */
>> +     writel(SSP_CTRL1_SSP_MODE_SD_MMC |
>> +             SSP_CTRL1_WORD_LENGTH_EIGHT_BITS |
>> +             SSP_CTRL1_DMA_ENABLE |
>> +             SSP_CTRL1_POLARITY |
>
> Will this addition not break mx28?

Not tested. I hope it does not as it has been taken from v3.7 kernel.

>> +             SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
>> +             SSP_CTRL1_DATA_CRC_IRQ_EN |
>> +             SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
>> +             SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
>> +             SSP_CTRL1_RESP_ERR_IRQ_EN,
>> +             &ssp_regs->hw_ssp_ctrl1_set);
>>
>>       /* Set initial bit clock 400 KHz */
>>       mxs_set_ssp_busclock(priv->id, 400);
>
> Best regards,
> Marek Vasut



--
Otavio Salvador                             O.S. Systems
E-mail: otavio at ossystems.com.br  http://www.ossystems.com.br
Mobile: +55 53 9981-7854              http://projetos.ossystems.com.br