[U-Boot] [PATCH 1/2] drivers/net/designware, do an explicit memory access instead of implicit, re-written assignments to use readl() and writel(), all of this as preperation for making the driver able to work in a cached environment (I$D$ support).

Frank Dols Frank.Dols at synopsys.com
Thu Jan 24 10:58:57 CET 2013


> Hi Vipin,
> On Wed, 23 Jan 2013 15:46:31 +0530, Vipin Kumar <vipin.kumar at st.com>
> wrote:
> >> My first feeling is that the descriptors are allocated as Normal  Cachabale memory and it would not help to access them using readl/writel
> >> ...
> > And no, we don't need to allocate them non-cacheable, although in this case we need to use cache flush and invalidate calls. I would 
> > suggest doing so rather than allocating the descriptors none cacheable, because using non-cacheable memory makes the dependency 
> > between the driver and cache codes implicit (and thus more prone to improperly thought out changes in either code) and the memory usage 
> > more complex, while explicit cache operations make the relationship explicit.
> Yes, got it. Thanks Albert
> Frank, so in that case rather changing the code to use readl/writel, cache flush and invalidate operations need to be performed at appropriate places
> Vipin
>> I believe patch 2/2 adds explicit cache ops, though I haven't read it in detail and thus don't know if everything needed is present and ok.
>> Amicalement, Albert.

Hi Vipin and Albert,
Sorry, I have to clarify here a bit more.
The descriptors are 16 bytes in length and a cache line is in most architectures more than 16 bytes in length (in our case either 32 or 64).
This means that cached accesses is not an option for these descriptors. Background, two adjacent descriptors as be on one cache line may be owned by different entities (host cpu / network ip).
Explicit cache calls that we are added in patch 2/2 are meant for payload of the package. And these are made cache line aligned with patch 1/2.
Unfortunately we can't align the descriptors on cache line boundaries due to hardware limitations (for architectures with cache line longer than 16 bytes) !
With kind regards, greetings, Frank.



More information about the U-Boot mailing list