[U-Boot] [PATCH 3/9] mx23: Fix transfer size setting for SPI

[Marek Vasut]

Dear Otavio Salvador,

NAK, this won't work. SSP0 DMA has this +1 offset in it's channel placement (so 
SSP0 DMA channel is actually channel 1), check the MMC patch.

> Signed-off-by: Otavio Salvador <otavio at ossystems.com.br>
> ---
>  drivers/spi/mxs_spi.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
> index bb865b7..10bf5aa 100644
> --- a/drivers/spi/mxs_spi.c
> +++ b/drivers/spi/mxs_spi.c
> @@ -167,8 +167,13 @@ static int mxs_spi_xfer_pio(struct mxs_spi_slave
> *slave, mxs_spi_start_xfer(ssp_regs);
> 
>  	while (length--) {
> +#if defined(CONFIG_MX23)
> +		writel(SSP_CTRL0_XFER_COUNT_MASK, &ssp_regs->hw_ssp_ctrl0_clr);
> +		writel(1, &ssp_regs->hw_ssp_ctrl0_set);
> +#elif defined(CONFIG_MX28)
>  		/* We transfer 1 byte */
>  		writel(1, &ssp_regs->hw_ssp_xfer_size);
> +#endif
> 
>  		if ((flags & SPI_XFER_END) && !length)
>  			mxs_spi_end_xfer(ssp_regs);

Best regards,
Marek Vasut