[U-Boot] [PATCH 1/2] Tegra114: fdt: Update DT files with I2C info for T114/Dalmore

[Tom Warren]

Note that T114 does not have a separate/different DVC (power I2C)
controller like T20 - all 5 I2C controllers are identical, but
I2C5 is used to designate the controller intended for power
control (PWR_I2C in the schematics).

Signed-off-by: Tom Warren <twarren at nvidia.com>
---
 arch/arm/dts/tegra114.dtsi            |   93 +++++++++++++++++++++++++++++++++
 board/nvidia/dts/tegra114-dalmore.dts |   33 ++++++++++++
 2 files changed, 126 insertions(+), 0 deletions(-)

diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi
index d06cd12..76fc83b 100644
--- a/arch/arm/dts/tegra114.dtsi
+++ b/arch/arm/dts/tegra114.dtsi
@@ -2,4 +2,97 @@
 
 / {
 	compatible = "nvidia,tegra114";
+
+	tegra_car: clock at 60006000 {
+		compatible = "nvidia,tegra114-car", "nvidia,tegra20-car";
+		reg = <0x60006000 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	apbdma: dma {
+		compatible = "nvidia,tegra114-apbdma", "nvidia,tegra20-apbdma";
+		reg = <0x6000a000 0x1400>;
+		interrupts = <0 104 0x04
+			      0 105 0x04
+			      0 106 0x04
+			      0 107 0x04
+			      0 108 0x04
+			      0 109 0x04
+			      0 110 0x04
+			      0 111 0x04
+			      0 112 0x04
+			      0 113 0x04
+			      0 114 0x04
+			      0 115 0x04
+			      0 116 0x04
+			      0 117 0x04
+			      0 118 0x04
+			      0 119 0x04
+			      0 128 0x04
+			      0 129 0x04
+			      0 130 0x04
+			      0 131 0x04
+			      0 132 0x04
+			      0 133 0x04
+			      0 134 0x04
+			      0 135 0x04
+			      0 136 0x04
+			      0 137 0x04
+			      0 138 0x04
+			      0 139 0x04
+			      0 140 0x04
+			      0 141 0x04
+			      0 142 0x04
+			      0 143 0x04>;
+	};
+
+	i2c at 7000c000 {
+		compatible = "nvidia,tegra114-i2c", "nvidia,tegra20-i2c";
+		reg = <0x7000c000 0x100>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		/* PERIPH_ID_I2C1 */
+		clocks = <&tegra_car 12>;
+	};
+
+	i2c at 7000c400 {
+		compatible = "nvidia,tegra114-i2c", "nvidia,tegra20-i2c";
+		reg = <0x7000c400 0x100>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		/* PERIPH_ID_I2C2 */
+		clocks = <&tegra_car 54>;
+	};
+
+	i2c at 7000c500 {
+		compatible = "nvidia,tegra114-i2c", "nvidia,tegra20-i2c";
+		reg = <0x7000c500 0x100>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		/* PERIPH_ID_I2C3 */
+		clocks = <&tegra_car 67>;
+	};
+
+	i2c at 7000c700 {
+		compatible = "nvidia,tegra114-i2c", "nvidia,tegra20-i2c";
+		reg = <0x7000c700 0x100>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		/* PERIPH_ID_I2C4 */
+		clocks = <&tegra_car 103>;
+	};
+
+	i2c at 7000d000 {
+		compatible = "nvidia,tegra114-i2c", "nvidia,tegra20-i2c";
+		reg = <0x7000d000 0x100>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		/* PERIPH_ID_I2C5 */
+		clocks = <&tegra_car 47>;
+	};
 };
diff --git a/board/nvidia/dts/tegra114-dalmore.dts b/board/nvidia/dts/tegra114-dalmore.dts
index 7315577..13b07f3 100644
--- a/board/nvidia/dts/tegra114-dalmore.dts
+++ b/board/nvidia/dts/tegra114-dalmore.dts
@@ -6,8 +6,41 @@
 	model = "NVIDIA Dalmore";
 	compatible = "nvidia,dalmore", "nvidia,tegra114";
 
+	aliases {
+		i2c0 = "/i2c at 7000d000";
+		i2c1 = "/i2c at 7000c000";
+		i2c2 = "/i2c at 7000c400";
+		i2c3 = "/i2c at 7000c500";
+		i2c4 = "/i2c at 7000c700";
+	};
+
 	memory {
 		device_type = "memory";
 		reg = <0x80000000 0x80000000>;
 	};
+
+	i2c at 7000c000 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c at 7000c400 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c at 7000c500 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c at 7000c700 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c at 7000d000 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
 };
-- 
1.7.0.4