[U-Boot] [PATCH 1/2] Tegra114: fdt: Update DT files with I2C info for T114/Dalmore

[Laxman Dewangan]

On Wednesday 30 January 2013 03:43 AM, Stephen Warren wrote:
> On 01/29/2013 02:57 PM, Tom Warren wrote:
>> Stephen,
>>
>> On Tue, Jan 29, 2013 at 2:08 PM, Stephen Warren <swarren at wwwdotorg.org> wrote:
>>> On 01/29/2013 01:40 PM, Tom Warren wrote:
>>>> Stephen,
>>>>
>>>> On Tue, Jan 29, 2013 at 1:09 PM, Stephen Warren <swarren at wwwdotorg.org> wrote:
>>>>> On 01/29/2013 12:19 PM, Tom Warren wrote:
>>>>>> Note that T114 does not have a separate/different DVC (power I2C)
>>>>>> controller like T20 - all 5 I2C controllers are identical, but
>>>>>> I2C5 is used to designate the controller intended for power
>>>>>> control (PWR_I2C in the schematics).
>>>>> If you do keep this node, it needs the clocks property filled in.
>>>>>
>>>>>> +     i2c at 7000c000 {
>>>>>> +             compatible = "nvidia,tegra114-i2c", "nvidia,tegra20-i2c";
>>>>> The I2C nodes also aren't backwards-compatible.
>>>> They were on T30 (same compatible string there, except of course
>>>> s/114/30/). And the tegra20-i2c is needed for fdtdec.c to find it
>>>> (compat_names table).
>>> Yes, I believe the HW changes between Tegra20 and Tegra30 were such that
>>> the Tegra20 driver would run unmodified on Tegra30 without issue. I
>>> don't believe that's the case for Tegra114 though. The solution would be
>>> to add the Tegra114 compatible value to the I2C driver so that it can
>>> search for both.
>> Looking at the TRMs for both T30 and T114, I2C looks nearly identical,
>> except for some additional registers tacked onto the end for bus clear
>> support. 99% of the bits appear exactly the same, too (with the
>> addition of a bus clear int bit on T114 in an used bit position).  I
>> know next to nothing about I2C, but it appears to me that the current
>> tegra_I2C.c driver should work fine on T114 (and does, since I can
>> probe addresses with it).  I don't see a need for a different driver
>> or compat value here.
> I Cc'd in Laxman here, since he wrote the Tegra114 I2C support for the
> kernel. He made the decision that Tegra114 I2C wasn't compatible with
> Tegra20/30 I2C, and can explain that. Certainly looking at the kernel
> patch I pointed at, it seems some of the clock divisors must be
> programmed differently, which certainly seems enough to declare the HW
> blocks incompatible, even if everything else is identical.
>

Tegra30 i2c driver will not work as straight. There is los of change 
which need to be taken care.

I posted the change for kernel driver.
Changes are:
- Enable/disable control for per packet transfer complete interrupt.
   Earlier SoCs could not disable this.
- Single clock source for standard/fast and HS mode clock speed.
   The clock divisor for fast/standard mode is added into the i2c
   controller to meet the HS and standard/fast mode of clock speed
   from single source.


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