[U-Boot] Question re HYP mode and IRQ/FIQ stack setting

[Andre Przywara]

On 11/12/2013 05:28 PM, Christoffer Dall wrote:
> On 12 November 2013 03:41, Albert ARIBAUD <albert.u.boot at aribaud.net> wrote:
>> (Cc:ing Andre and Christoffer as they have discussed HYP on the ML.)
>>
>> Hello,
>>
>> I am working on changing the way IRQ/FIQ stacks are set up, from
>> "on-the-fly in a hurry while in the handler" to "during init, so that
>> when entering the handler, the stack is already correct".
>>
>> Setting the stack then requires switching from the current mode (in
>> most cases, SVC32, 0x13) to IRQ (0x11) or FIQ (0x12) mode, in order to
>> set the right banked SP, then back into the original mode.
>>
>> However, in the first lines of reset in arch/arm/cpu/armv7/start.S, the
>> possibility of U-Boot being started in HYP mode (0x1A) is considered
>> and, if in HYP mode, no switch to SVC32 is performed.
>>
>> I understand that the problem here is, if we drop from HYP to SVC32,
>> then we cannot go back to HYP, and we want to be able to remain in HYP.

Right, that is to keep the HYP mode in case the firmware already enabled 
it. This is for instance the case on the new Calxeda Midway. Actually 
this approach will become more widespread, since it is required to 
provide proper PSCI support (which needs to run in secure state, so 
requires an even higher privilege level than HYP: EL3 in the new ARM speak).

> correct (not without setting up a trap handler in Hyp mode and
> trapping to Hyp mode)
>
>>
>> Does this also apply to dropping from HYP to IRQ or FIQ mode, i.e., if
>> we do such a drop, are we prevented from rising back from IRQ or FIQ
>> mode to HYP? I seem to remember such an issue, but I am no specialist
>> in HYP, so any help is welcome.
>
> Yes, it also applies.  Hyp is strictly more privileged (PL2) than all
> the PL1 modes (SVC, SYS, IRQ, FIQ, ABT, UND) and therefore requires a
> trap to go from PL1 to PL2 (basically this is how hardware protection
> works - just like with syscalls from user mode to PL1).

Thanks Christoffer for clarifying this, I wasn't sure about FIQ, but of 
course your explanation (EL1 vs. EL2) makes totally sense.

But I wonder what happens when we enter FIQ or IRQ due to an actual 
interrupt. Will the CPU return into HYP mode when the handler returns?
That is subject to some HYP mode register configuration, right?

> You can use MSR and MRS instructions to access the IRQ and FIQ
> registers directly from Hyp mode though.

Albert,
so does "msr sp_{fiq,irq}, r<n>" fix your problem? Or do you still need 
to actually go into one of these modes for further setup?

Regards,
Andre.