[U-Boot] Question re HYP mode and IRQ/FIQ stack setting

[Christoffer Dall]

On 12 November 2013 08:53, Andre Przywara <andre.przywara at linaro.org> wrote:
> On 11/12/2013 05:28 PM, Christoffer Dall wrote:
>>
>> On 12 November 2013 03:41, Albert ARIBAUD <albert.u.boot at aribaud.net>
>> wrote:
>>>
>>> (Cc:ing Andre and Christoffer as they have discussed HYP on the ML.)
>>>
>>> Hello,
>>>
>>> I am working on changing the way IRQ/FIQ stacks are set up, from
>>> "on-the-fly in a hurry while in the handler" to "during init, so that
>>> when entering the handler, the stack is already correct".
>>>
>>> Setting the stack then requires switching from the current mode (in
>>> most cases, SVC32, 0x13) to IRQ (0x11) or FIQ (0x12) mode, in order to
>>> set the right banked SP, then back into the original mode.
>>>
>>> However, in the first lines of reset in arch/arm/cpu/armv7/start.S, the
>>> possibility of U-Boot being started in HYP mode (0x1A) is considered
>>> and, if in HYP mode, no switch to SVC32 is performed.
>>>
>>> I understand that the problem here is, if we drop from HYP to SVC32,
>>> then we cannot go back to HYP, and we want to be able to remain in HYP.
>
>
> Right, that is to keep the HYP mode in case the firmware already enabled it.
> This is for instance the case on the new Calxeda Midway. Actually this
> approach will become more widespread, since it is required to provide proper
> PSCI support (which needs to run in secure state, so requires an even higher
> privilege level than HYP: EL3 in the new ARM speak).
>

What Andre is referring to here is that the PSCI specs mandates the
CPUs that a are turned on using PSCI go through the highest privilege
level implemented in the non-secure state.  I couldn't actually find
the place in the PSCI specs where this is also true for the boot CPU,
but granted, anything else will be quite strange.

So to stay in 32-bit ARMv7 terminology here, a likely case for systems
with PSCI support in the firmware is that all cores will enter U-Boot
in non-secure PL2 (hyp) mode and power management is done by calling
SMC calls to the firmware that sits in the secure monitor.

>
>> correct (not without setting up a trap handler in Hyp mode and
>> trapping to Hyp mode)
>>
>>>
>>> Does this also apply to dropping from HYP to IRQ or FIQ mode, i.e., if
>>> we do such a drop, are we prevented from rising back from IRQ or FIQ
>>> mode to HYP? I seem to remember such an issue, but I am no specialist
>>> in HYP, so any help is welcome.
>>
>>
>> Yes, it also applies.  Hyp is strictly more privileged (PL2) than all
>> the PL1 modes (SVC, SYS, IRQ, FIQ, ABT, UND) and therefore requires a
>> trap to go from PL1 to PL2 (basically this is how hardware protection
>> works - just like with syscalls from user mode to PL1).
>
>
> Thanks Christoffer for clarifying this, I wasn't sure about FIQ, but of
> course your explanation (EL1 vs. EL2) makes totally sense.
>
> But I wonder what happens when we enter FIQ or IRQ due to an actual
> interrupt. Will the CPU return into HYP mode when the handler returns?
> That is subject to some HYP mode register configuration, right?
>

Not quite, interrupts in Hyp mode will always be taken to Hyp mode
(unless it's secure interrupts, which are taken to monitor mode).  In
fact, when you have the virtualization extensions, you also have the
security extensions, and I think all FIQs go to the secure mode here,
so you can't ever see an FIQ in Hyp mode.  I may be mistaken here,
someone should look it up and verify.

Now, you can configure Hyp mode to trap interrupts raised while in any
PL1 or PL0 mode to Hyp mode.

I suspect that if you are in Hyp mode, you should not worry about
FIQ/IRQ mode, but just make sure to configure Hyp mode properly to
handle interrupts.  (it's a separate entry in the exception vector and
you probably need to look at the HSR register whn you've taken an
interrupt).  So, as Andre suggests below, it depends on your use case.

>
>> You can use MSR and MRS instructions to access the IRQ and FIQ
>> registers directly from Hyp mode though.
>
>
> Albert,
> so does "msr sp_{fiq,irq}, r<n>" fix your problem? Or do you still need to
> actually go into one of these modes for further setup?
>
> Regards,
> Andre.
>