[U-Boot] i2c issues with efikamx and mainline uboot

[Benoît Thébaudeau]

Dear Konstantinos Margaritis,

On Thursday, November 21, 2013 12:15:18 AM, Konstantinos Margaritis wrote:
> On Tue, 19 Nov 2013 18:02:19 +0100 (CET)
> Benoît Thébaudeau <benoit.thebaudeau at advansee.com> wrote:
> > I use the i.MX515, and the I²C worked fine at some point in mainline
> > U-Boot. If it does not work for you now, it's either because of a
> > software regression, or because of some board-specific issue, e.g.
> > pads. SION may have to be set for I²C.
> 
> Hi Benoît,
> 
> By "SION may have to be set for I²C", do you mean that
> IOMUX_CONFIG_SION might have to be defined and ORed in the MX51 pads
> in arch/arm/include/asm/arch-mx5/iomux-mx51.h just is it is set in
> arch/arm/include/asm/arch-mx5/iomux-mx53.h, for example:
> 
> MX53_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x364, 0x03C, 4 |
> IOMUX_CONFIG_SION, 0x81C, 0, NO_PAD_CTRL),

Correct.

> How do I know in which ones do I have to set SION? I've added some
> pad defines in the mx51 file, needed for LCD bringup, and I hope I did
> it the right way -at least I followed the RM as close as I could and
> Marek was of tremendous help here, but I didn't even know about that
> SION thing while doing that. I'd gladly try it out, before following
> Fabio's advice and try to merge the patches to the u-boot-imx tree
> -tried already but they don't apply cleanly, I'll have to do it when I
> get more free time, most likely during the weekend.

The normal rule is that SION is required whenever a pin is in input and output
at the same time. E.g., this is the case when you want to read the actual level
on a GPIO pin in output mode. This is also the case for both I²C pins (SDA and
SCL):
 - SDA is either the master or the slave output depending on the time slot,
 - SCL may be stretched by the slave if it is too slow compared to the master
   requests.
In both cases, the pad may set some level, but the IP also needs to read back
the actual level in order to work correctly. Also make sure that SDA and SCL are
configured in open drain mode, and that there is a pull-up (either enabled in
the SoC pad, or as an external resistor on the board) on both.

Best regards,
Benoît