[U-Boot] [PATCH] powerpc/mpc85xx: Add workaround for erratum A006379

[York Sun]

Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default
value after POR. The workaround is to set this field before enabling
CPC to 0x1e.

Signed-off-by: York Sun <yorksun at freescale.com>
---
 arch/powerpc/cpu/mpc85xx/cmd_errata.c     |    8 ++++++++
 arch/powerpc/cpu/mpc85xx/cpu_init.c       |   11 +++++++++++
 arch/powerpc/include/asm/config_mpc85xx.h |    5 +++++
 arch/powerpc/include/asm/immap_85xx.h     |    1 +
 4 files changed, 25 insertions(+)

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index c441bd2..a78e227 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -245,6 +245,14 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
 	puts("Work-around for Erratum A006593 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006379
+	if (
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006379_SVR_REV2
+	    ((svr & 0xff) == CONFIG_SYS_FSL_ERRATUM_A006379_SVR_REV2) ||
+#endif
+	    ((svr & 0xff) == CONFIG_SYS_FSL_ERRATUM_A006379_SVR_REV))
+		puts("Work-around for Erratum A006379 enabled\n");
+#endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
 	if (IS_SVR_REV(svr, 1, 0))
 		puts("Work-around for Erratum A003571 enabled\n");
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 6036333..aff8cec 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -126,6 +126,7 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm)
 #ifdef CONFIG_SYS_FSL_CPC
 static void enable_cpc(void)
 {
+	 __maybe_unused u32 svr = get_svr();
 	int i;
 	u32 size = 0;
 
@@ -160,6 +161,16 @@ static void enable_cpc(void)
 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
 		setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006379
+		if (
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006379_SVR_REV2
+		    ((svr & 0xff) == CONFIG_SYS_FSL_ERRATUM_A006379_SVR_REV2) ||
+#endif
+		    ((svr & 0xff) == CONFIG_SYS_FSL_ERRATUM_A006379_SVR_REV)) {
+			setbits_be32(&cpc->cpchdbcr0,
+				     CPC_HDBCR0_SPLRU_LEVEL_EN);
+		}
+#endif
 
 		out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
 		/* Read back to sync write */
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index bec8966..83684cf 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -593,6 +593,8 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004468
 #define CONFIG_SYS_FSL_ERRATUM_A_004934
 #define CONFIG_SYS_FSL_ERRATUM_A005871
+#define CONFIG_SYS_FSL_ERRATUM_A006379
+#define CONFIG_SYS_FSL_ERRATUM_A006379_SVR_REV	0x10
 #define CONFIG_SYS_FSL_ERRATUM_A006593
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_PCI_VER_3_X
@@ -617,6 +619,9 @@
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_ERRATUM_A_004934
 #define CONFIG_SYS_FSL_ERRATUM_A005871
+#define CONFIG_SYS_FSL_ERRATUM_A006379
+#define CONFIG_SYS_FSL_ERRATUM_A006379_SVR_REV	0x10
+#define CONFIG_SYS_FSL_ERRATUM_A006379_SVR_REV2	0x20
 #define CONFIG_SYS_FSL_ERRATUM_A006593
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 3a10d77..a938143 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1671,6 +1671,7 @@ typedef struct cpc_corenet {
 #define CPC_HDBCR0_CDQ_SPEC_DIS	0x08000000
 #define CPC_HDBCR0_TAG_ECC_SCRUB_DIS	0x01000000
 #define CPC_HDBCR0_DATA_ECC_SCRUB_DIS	0x00400000
+#define CPC_HDBCR0_SPLRU_LEVEL_EN	0x003c0000
 #endif /* CONFIG_SYS_FSL_CPC */
 
 /* Global Utilities Block */
-- 
1.7.9.5