[U-Boot] [RFC 5/5] B4860QDS: Add support of 2 stage NAND boot loader
Prabhakar Kushwaha
prabhakar at freescale.com
Mon Sep 16 18:05:43 CEST 2013
Add support of 2 stage NAND boot loader using SPL framework.
here, PBL initialise the internal SRAM and copy SPL(96K). This further
initialise DDR using SPD and environment and copy u-boot(512 kb) from NAND to DDR.
Finally SPL transer control to u-boot.
Initialise/create followings required for SPL framework
- Add spl.c which defines board_init_f, board_init_r
- update tlb and ddr accordingly
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
---
This is a prototype done on B4860.It has 512K internal RAM.
We only configured SRAM as 256K and made sure only 128KB is used
throught SPL execution.
board/freescale/b4860qds/Makefile | 7 +-
board/freescale/b4860qds/ddr.c | 6 +-
board/freescale/b4860qds/spl.c | 128 +++++++++++++++++++++++++++++++++++++
board/freescale/b4860qds/tlb.c | 10 +++
boards.cfg | 2 +-
include/configs/B4860QDS.h | 58 +++++++++++++++--
6 files changed, 203 insertions(+), 8 deletions(-)
create mode 100644 board/freescale/b4860qds/spl.c
diff --git a/board/freescale/b4860qds/Makefile b/board/freescale/b4860qds/Makefile
index a864c0b..42819a6 100644
--- a/board/freescale/b4860qds/Makefile
+++ b/board/freescale/b4860qds/Makefile
@@ -8,10 +8,15 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
+ifdef CONFIG_SPL_BUILD
+COBJS-y += spl.o
+endif
+ifndef CONFIG_SPL_BUILD
COBJS-y += $(BOARD).o
-COBJS-y += ddr.o
COBJS-$(CONFIG_B4860QDS)+= eth_b4860qds.o
COBJS-$(CONFIG_PCI) += pci.o
+endif
+COBJS-y += ddr.o
COBJS-y += law.o
COBJS-y += tlb.o
diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c
index b82b3d4..467be3c 100644
--- a/board/freescale/b4860qds/ddr.c
+++ b/board/freescale/b4860qds/ddr.c
@@ -181,12 +181,16 @@ phys_size_t initdram(int board_type)
puts("Initializing....using SPD\n");
+#ifdef CONFIG_SPL_BUILD
dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
- puts(" DDR: ");
+#else
+ puts("DDR has been initialised by pre loader\n");
+ dram_size = 0x80000000;
+#endif
return dram_size;
}
diff --git a/board/freescale/b4860qds/spl.c b/board/freescale/b4860qds/spl.c
new file mode 100644
index 0000000..55891fc
--- /dev/null
+++ b/board/freescale/b4860qds/spl.c
@@ -0,0 +1,128 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <ns16550.h>
+#include <asm/spl.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <malloc.h>
+#include <nand.h>
+#include <i2c.h>
+#include "../common/qixis.h"
+#include "b4860qds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+ulong get_effective_memsize(void)
+{
+ return CONFIG_SYS_L3_SIZE;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch ((sysclk_conf & 0x0C) >> 2) {
+ case QIXIS_CLK_100:
+ return 100000000;
+ case QIXIS_CLK_125:
+ return 125000000;
+ case QIXIS_CLK_133:
+ return 133333333;
+ }
+ return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch (ddrclk_conf & 0x03) {
+ case QIXIS_CLK_100:
+ return 100000000;
+ case QIXIS_CLK_125:
+ return 125000000;
+ case QIXIS_CLK_133:
+ return 133333333;
+ }
+ return 66666666;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio, sys_clk, uart_clk;
+ u32 stack = CONFIG_SPL_RELOC_STACK;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ console_init_f();
+
+ /* initialize selected port with appropriate baud rate */
+ sys_clk = get_board_sys_clk();
+ /* plat_ratio = 10; */
+ plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
+ uart_clk = sys_clk * plat_ratio / 2;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ uart_clk / 16 / CONFIG_BAUDRATE);
+
+ /* clear BSS segment */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* Set STACK pointer */
+ asm volatile ("lwz 1, %0" : : "m"(stack));
+
+ board_init_r(NULL, 0x0);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ /* Pointer is writable since we allocated a register for it */
+ gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+ bd_t *bd;
+
+ memset(gd, 0, sizeof(gd_t));
+ bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+ memset(bd, 0, sizeof(bd_t));
+ gd->bd = bd;
+ bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
+ bd->bi_memsize = CONFIG_SYS_L3_SIZE;
+
+ probecpu();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+ CONFIG_SPL_RELOC_MALLOC_SIZE);
+ env_init();
+
+ /* relocate environment function pointers etc. */
+ env_relocate();
+
+ i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE);
+
+ gd->ram_size = initdram(0);
+ puts("Second program loader running in sram...\n");
+
+#ifdef CONFIG_SPL_NAND_BOOT
+ nand_boot();
+#endif
+}
diff --git a/board/freescale/b4860qds/tlb.c b/board/freescale/b4860qds/tlb.c
index f71aca4..734b1e3 100644
--- a/board/freescale/b4860qds/tlb.c
+++ b/board/freescale/b4860qds/tlb.c
@@ -62,6 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
+#ifndef CONFIG_SPL_BUILD
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -96,6 +97,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 9, BOOKE_PAGESZ_16M, 1),
#endif
+#endif
#ifdef CONFIG_SYS_DCSRBAR_PHYS
SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -118,6 +120,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* entry 14 and 15 has been used hard coded, they will be disabled
* in cpu_init_f, so we use entry 16 for SRIO2.
*/
+#ifndef CONFIG_SPL_BUILD
#ifdef CONFIG_SYS_SRIO1_MEM_PHYS
/* *I*G* - SRIO1 */
SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS,
@@ -140,6 +143,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
0, 17, BOOKE_PAGESZ_1M, 1),
#endif
+#endif
+
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 17, BOOKE_PAGESZ_2G, 1)
+#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/boards.cfg b/boards.cfg
index b4297e5..824d77d 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -950,7 +950,7 @@ T4160QDS powerpc mpc85xx t4qds freesca
T4160QDS_SDCARD powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
T4160QDS_SPIFLASH powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
B4860QDS powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4860
-B4860QDS_NAND powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
+B4860QDS_NAND powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND
B4860QDS_SPIFLASH powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
B4860QDS_SRIO_PCIE_BOOT powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
B4420QDS powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4420
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 2f0bc6b..0fef305 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -14,8 +14,41 @@
#define CONFIG_PHYS_64BIT
#ifdef CONFIG_RAMBOOT_PBL
+#ifndef CONFIG_NAND
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#else
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+#define CONFIG_SKIP_RELOCATE_SPL
+#define CONFIG_SYS_TEXT_BASE 0x00201000
+#define CONFIG_SPL_TEXT_BASE 0xfffe8000
+#define CONFIG_SPL_PAD_TO 0x18000
+#define CONFIG_SPL_MAX_SIZE 0x18000
+#define RESET_VECTOR_OFFSET 0x17FFC
+#define BOOT_PAGE_OFFSET 0x17000
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (512 << 10)
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#define CONFIG_SPL_NAND_BOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#define CONFIG_SYS_NO_FLASH
+#endif
+#define CONFIG_RAMBOOT_TEXT_BASE 0xFFF80000
+#endif
#endif
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
@@ -112,8 +145,8 @@
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_SIZE 0x1000
+#define CONFIG_ENV_OFFSET (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
#define CONFIG_ENV_IS_IN_REMOTE
#define CONFIG_ENV_ADDR 0xffe20000
@@ -163,7 +196,14 @@ unsigned long get_board_ddr_clk(void);
/*
* Config the L3 Cache as L3 SRAM
*/
-#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
+#define CONFIG_SYS_L3_SIZE 512 << 10
+#define CONFIG_SYS_INIT_L3_ADDR 0xFFFE0000
+#define CONFIG_SPL_RELOC_TEXT_BASE CONFIG_SYS_INIT_L3_ADDR
+#define CONFIG_SPL_GD_ADDR CONFIG_SYS_INIT_L3_ADDR
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L3_ADDR + 1 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (26 << 10)
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE (5 << 10)
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_DCSRBAR 0xf0000000
@@ -192,7 +232,9 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_DDR_SPD
#define CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_FSL_DDR3
+#ifndef CONFIG_SPL_BUILD
#define CONFIG_FSL_DDR_INTERACTIVE
+#endif
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS1 0x51
@@ -378,7 +420,11 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
#if defined(CONFIG_RAMBOOT_PBL)
#define CONFIG_SYS_RAMBOOT
@@ -432,7 +478,9 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
#define CONFIG_SERIAL_MULTI /* Enable both serial ports */
+#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
+#endif
/* Use the HUSH parser */
@@ -604,7 +652,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_QE_FMAN_FW_ADDR (9 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* Slave has no ucode locally, it can fetch this from remote. When implementing
--
1.7.9.5
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