[U-Boot] [RFC 5/5] B4860QDS: Add support of 2 stage NAND boot loader

[Rommel Custodio]

Dear Prabhakar Kushwaha,

Prabhakar Kushwaha <prabhakar <at> freescale.com> writes:

> 
> Add support of 2 stage NAND boot loader using SPL framework.
> here, PBL initialise the internal SRAM and copy SPL(96K). This further
> initialise DDR using SPD and environment and copy u-boot(512 kb) from NAND 
to DDR.
> Finally SPL transer control to u-boot.


These are just some quick comments after a build test and a quick code 
review.
The environment is latest with some patches from patchworks.

1) Your code does not build with
http://patchwork.ozlabs.org/patch/274193/

powerpc-linux-objcopy --gap-fill=0xff -O binary 
/export/home/git.denx.de/local/obj-B4860QDS_NAND/u-boot 
/export/home/git.denx.de/local/obj-B4860QDS_NAND/u-boot.bin
/export/home/git.denx.de/local/obj-B4860QDS_NAND/tools/mkimage -n  \
                -R  -T pblimage \
                -d /export/home/git.denx.de/local/obj-B4860QDS_NAND/u-
boot.bin /export/home//git.denx.de/local/obj-B4860QDS_NAND/u-boot.pbl
Error:-R - Can't open
make: *** [/export/home/git.denx.de/local/obj-B4860QDS_NAND/u-boot.pbl] 
Error 1

You mention you use the PBL... but probably not a pblimage. The patch 
correctly fixes RAMBOOT_PBL as a trigger to generate the pblimage (u-
boot.pbl) but there seems to be no RCW or PBI file defined.


2) Use the new SPDX identifiers
http://patchwork.ozlabs.org/patch/261356/

This was mainlined a few revisions ago.


3) Watch out for the new boards.cfg layout



I have one question, can this scenario be implemented on a P5040? i.e. 
simulate that CPC is around 128Kb and load u-boot via SPL? Now all corenet 
processors seem to only support pblimage booting.

All the best,
Rommel