[U-Boot] [PATCH 10/10] board/t104xrdb: Add support of NAND, SD, SPI boot for T1040RDB

[Prabhakar Kushwaha]

On 4/1/2014 4:40 AM, Rommel G Custodio wrote:
> Dear Prabhakar Kushwaha,
>
> Prabhakar Kushwaha <prabhakar <at> freescale.com> writes:
>
>> Add support of 2 stage NAND, SD, SPI boot loader using SPL framework.
>> here, PBL initialise the internal SRAM and copy SPL(160KB). This further
>> initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND
> to DDR.
>> Finally SPL transer control to u-boot.
> This patch does not apply to HEAD.
>
> [u-boot (X_2stage $)]$ pw_u.sh 335250
> 2014-04-01 07:11:13 URL:http://patchwork.ozlabs.org/patch/335250/mbox/
> [23256] -> "pw-am-335250.patch" [1]
> Applying: board/t104xrdb: Add support of NAND, SD, SPI boot for T1040RDB
> error: patch failed: boards.cfg:933
> error: boards.cfg: patch does not apply
> error: include/configs/T104xRDB.h: does not exist in index
>
>
> More comments below.
>
> 8>< snipped ><8
>
>> diff --git a/board/freescale/t104xrdb/t1040_rcw.cfg
> b/board/freescale/t104xrdb/t1040_rcw.cfg
>> new file mode 100644
>> index 0000000..3300c18
>> --- /dev/null
>> +++ b/board/freescale/t104xrdb/t1040_rcw.cfg
>>   <at>  <at>  -0,0 +1,7  <at>  <at>
>> +#PBL preamble and RCW header
>> +aa55aa55 010e0100
>> +# serdes protocol 0x66
>> +0c18000e 0e000000 00000000 00000000
>> +66000002 80000002 e8106000 01000000
> e8106000
> ^^^^^^^^
> Don't you need a separate RCW setting for SPI?
> The previous patchset had a note about it.
>

You can change.
Generally switch has higher precedence over  PBI_SRC in RCW.


>> +00000000 00000000 00000000 00032810
>> +00000000 0342500f 00000000 00000000
>> diff --git a/board/freescale/t104xrdb/t1042_rcw.cfg
> b/board/freescale/t104xrdb/t1042_rcw.cfg
>> new file mode 100644
>> index 0000000..a3ea8ad
>> --- /dev/null
>> +++ b/board/freescale/t104xrdb/t1042_rcw.cfg
>>   <at>  <at>  -0,0 +1,7  <at>  <at>
>> +#PBL preamble and RCW header
>> +aa55aa55 010e0100
>> +# serdes protocol 0x66
>> +0c18000e 0e000000 00000000 00000000
>> +06000002 00400002 e8106000 01000000
>> +00000000 00000000 00000000 00030810
>> +00000000 01fe0a06 00000000 00000000
>> diff --git a/board/freescale/t104xrdb/t104x_pbi.cfg
> b/board/freescale/t104xrdb/t104x_pbi.cfg
>> new file mode 100644
>> index 0000000..7b9e9b0
>> --- /dev/null
>> +++ b/board/freescale/t104xrdb/t104x_pbi.cfg
>>   <at>  <at>  -0,0 +1,26  <at>  <at>
>> +#PBI commands
>> +#Initialize CPC1
>> +09010000 00200400
>> +09138000 00000000
>> +091380c0 00000100
>> +#Configure CPC1 as 256KB SRAM
>> +09010100 00000000
>> +09010104 fffc0007
>> +09010f00 08000000
>> +09010000 80000000
>> +#Configure LAW for CPC1
>> +09000cd0 00000000
>> +09000cd4 fffc0000
>> +09000cd8 81000011
>> +#Configure alternate space
>> +09000010 00000000
>> +09000014 ff000000
>> +09000018 81000000
>> +#Configure SPI controller
>> +09110000 80000403
>> +09110020 2d170008
>> +09110024 00100008
>> +09110028 00100008
>> +0911002c 00100008
>> +#Flush PBL data
>> +091380c0 000FFFFF
> That's a "Wait" command.
> Unless the "Flush" was command (that is in most PBI files I've read,
> Flush/Wait pait) was inadvertantly deleted.
>

Flush command only work for CCSRBAR address space. It should not be used 
for CPC-SRAM.

This is the reason, it has been removed.

Regards,
Prabhakar