[U-Boot] [PATCH] ARMv8: fix bug for flush data cache by set/way

[Leo Yan]

hi David,

> On 04/01/2014 11:25 AM, fenghua at phytium.com.cn wrote:
>> hi Leo,
>>         Please reference ARMv8-TRM, the associativity field does not have
>> to be a power of 2. I made the same mistake with you previously and
>>    scott identify this.
>>
>> *发件人:* Leo Yan <mailto:leoy at marvell.com>
>> *发送时间:* ‎2014‎年‎3‎月‎31‎日, ‎星期一 ‎9‎:‎11
>> *收件人:* u-boot <mailto:u-boot at lists.denx.de>, David Feng
>> <mailto:fenghua at phytium.com.cn>, Scott Wood <mailto:scottwood at freescale.com>
>> *抄送:* Leo Yan <mailto:leoy at marvell.com>
>>
>> When flush the d$ with set/way instruction, it need calculate the way's
>> offset = log2(Associativity); but in current uboot's code, it use below
>> formula to calculate the offset: log2(Associativity * 2 - 1), so finally
>> it cannot flush data cache properly.
>>
>> Signed-off-by: Leo Yan <leoy at marvell.com>
>> ---
>>    arch/arm/cpu/armv8/cache.S |    4 +---
>>    1 file changed, 1 insertion(+), 3 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S
>> index 546a83e..256d2e2 100644
>> --- a/arch/arm/cpu/armv8/cache.S
>> +++ b/arch/arm/cpu/armv8/cache.S
>> @@ -30,9 +30,7 @@ ENTRY(__asm_flush_dcache_level)
>>     add x2, x2, #4  /* x2 <- log2(cache line size) */
>>     mov x3, #0x3ff
>>     and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */
>> - add w4, w3, w3
>> - sub w4, w4, 1  /* round up log2(#ways + 1) */
>> - clz w5, w4   /* bit position of #ways */
>> + clz w5, w3   /* bit position of #ways */
>>     mov x4, #0x7fff
>>     and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */
>>     /* x1 <- cache level << 1 */
>> --
>> 1.7.9.5
>>

Apologize for top post in previous email, resend the email again.

I have checked the ARMv8's Architecture Reference Manual 
DDI0487A_a_armv8_arm.pdf chapter "C4.4.1 DC CISW, Data or unified Cache 
line Clean and Invalidate by Set/Way", u can see the description as below:

SetWay, bits [31:4]
Contains two fields:
   • Way, bits[31:32-A], the number of the way to operate on.
   • Set, bits[B-1:L], the number of the set to operate on.
Bits[L-1:4] are RES0.
A = Log2(ASSOCIATIVITY), L = Log2(LINELEN), B = (L + S), S = 
Log2(NSETS). ASSOCIATIVITY, LINELEN (line length, in bytes), and NSETS 
(number of sets) have their usual meanings and are the values for the 
cache level being operated on. The values of A and S are rounded up to 
the next integer.

Also we have tested on ARMv8's soc, we found this issue will introduce 
the cache cannot flush properly into DDR so that kernel cannot boot up 
successfully.

BTW, i compared with Linux kernel's code for flushing operations and 
just commit this patch to align with it.

Thx,
Leo Yan