[U-Boot] [PATCH][v3] powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDS

[Wolfgang Denk]

Dear Aneesh Bansal,

In message <1391419033-14283-1-git-send-email-aneesh.bansal at freescale.com> you wrote:
> Changes:
> 1. L2 cache is being invalidated by Boot ROM code for e6500 core.
>    So removing the invalidation from start.S
> 2. Clear the LAW and corresponding configuration for CPC. Boot ROM
>    code uses it as hosekeeping area.
> 3. For Secure boot, CPC is configured as SRAM and used as house
>    keeping area. This configuration is to be disabled once in uboot.
>    Earlier this disabling of CPC as SRAM was happening in cpu_init_r.
>    As a result cache invalidation function was getting skipped in
>    case CPC is configured as SRAM.This was causing random crashes.
...
> +#if defined(CONFIG_RAMBOOT_PBL)
> +	disable_cpc_sram();
> +#endif

What is the meaning of this undocumented CONFIG_RAMBOOT_PBL option?

As far as I understand, this is not a boot from RAM at all, but a
totally normal step in a boot process form regular boot media?

Best regards,

Wolfgang Denk

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