[U-Boot] [PATCH][v3] powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDS

[Scott Wood]

On Mon, 2014-02-03 at 19:58 +0100, Wolfgang Denk wrote:
> Dear Aneesh Bansal,
> 
> In message <1391419033-14283-1-git-send-email-aneesh.bansal at freescale.com> you wrote:
> > Changes:
> > 1. L2 cache is being invalidated by Boot ROM code for e6500 core.
> >    So removing the invalidation from start.S
> > 2. Clear the LAW and corresponding configuration for CPC. Boot ROM
> >    code uses it as hosekeeping area.
> > 3. For Secure boot, CPC is configured as SRAM and used as house
> >    keeping area. This configuration is to be disabled once in uboot.
> >    Earlier this disabling of CPC as SRAM was happening in cpu_init_r.
> >    As a result cache invalidation function was getting skipped in
> >    case CPC is configured as SRAM.This was causing random crashes.
> ...
> > +#if defined(CONFIG_RAMBOOT_PBL)
> > +	disable_cpc_sram();
> > +#endif
> 
> What is the meaning of this undocumented CONFIG_RAMBOOT_PBL option?

I agree it should be documented, but it's not new to this patch.

> As far as I understand, this is not a boot from RAM at all, but a
> totally normal step in a boot process form regular boot media?

FWIW, the only documentation I can find for CONFIG_SYS_RAMBOOT is
doc/README.mpc85xx and doc/README.ramboot-ppc85xx which specify its
usage in "totally normal steps in a boot process from regular boot
media".

Any instance of "booting from RAM" is going to need the image to get
into RAM somehow.  If the symbol is to mean anything at all, it seems
reasonable that it means that U-Boot was executing from RAM when the
current image was entered, regardless of how that came to be.  There
should be some way to distinguish running from SRAM versus running from
DDR, though.

-Scott