[U-Boot] [PATCH 0/4] Add LS1021A-QDS/TWR Non-secure and HYP support.

[Li.Xiubo at freescale.com]

> > This patch series depends on the following patch:
> >
> > [U-Boot,v4,03/10] ARM: non-sec: reset CNTVOFF to zero
> >
> > Before switching to non-secure, make sure that CNTVOFF is set
> > to zero on all CPUs. Otherwise, kernel running in non-secure
> > without HYP enabled (hence using virtual timers) may observe
> 
> But we have HYP enabled. In this case why are the series dependent on
> this patch?
> 

Well, if the HYP is enabled, the host OS will use the Physical timer,
and these CNTVOFFs could be cleared in kernel too.

When and where to clear them is better ? In uboot or in kernel when needed?


Thanks,

BRs
Xiubo




> > timers that are not synchronized, effectively seeing time
> > going backward...
> >
> >
> >
> > Patch work:
> > http://patchwork.ozlabs.org/patch/343084/
> >
> >
> >
> >
> >
> > Xiubo Li (4):
> >    ARM: fix the ARCH Timer frequency setting.
> >    ARM: add the pen address byte reverting support.
> >    ARM: LS1021A: enable ARMv7 virt support for LS1021A A7
> >    ARM: LS1021A: to allow non-secure R/W access for all devices' mapped
> >      region
> >
> >   arch/arm/cpu/armv7/ls102xa/cpu.c                  |  12 +++
> >   arch/arm/cpu/armv7/nonsec_virt.S                  |   7 +-
> >   arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  98 +++++++++++++++++-
> -
> >   board/freescale/ls1021aqds/ls1021aqds.c           | 110
> +++++++++++++++++++--
> >   board/freescale/ls1021atwr/ls1021atwr.c           | 111
> ++++++++++++++++++++--
> >   include/configs/ls1021aqds.h                      |   9 ++
> >   include/configs/ls1021atwr.h                      |   9 ++
> >   7 files changed, 333 insertions(+), 23 deletions(-)
> 
> Diana