[U-Boot] [PATCH v1 7/7] board/ti/dra7xx: add support for parallel NAND

Pekon Gupta pekon at ti.com
Fri Jul 4 21:05:17 CEST 2014


This patch adds support for x16 NAND device (MT29F2G16AAD) connected to GPMC
chip-select present on DRA7xx EVM.
On this board, GPMC_WPN and NAND_BOOTn are controlled by DIP switch,
So following board settings are required for NAND device detection:
  SW5.9 (GPMC_WPN) = LOW
  SW5.1 (NAND_BOOTn) = HIGH

Signed-off-by: Pekon Gupta <pekon at ti.com>
---
 board/ti/dra7xx/mux_data.h   | 30 +++++++++++++++++++++++
 boards.cfg                   |  2 +-
 include/configs/dra7xx_evm.h | 58 +++++++++++++++++++++++++++++++++++++++++++-
 3 files changed, 88 insertions(+), 2 deletions(-)

diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index 38de9d5..697e9e4 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -51,6 +51,35 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
 	{RGMII0_RXD2, (IEN | M0) },
 	{RGMII0_RXD1, (IEN | M0) },
 	{RGMII0_RXD0, (IEN | M0) },
+#ifdef CONFIG_NAND
+	/* NAND / NOR pin-mux */
+	{GPMC_AD0 , M0 | IEN | PDIS}, /* AD0  */
+	{GPMC_AD1 , M0 | IEN | PDIS}, /* AD1  */
+	{GPMC_AD2 , M0 | IEN | PDIS}, /* AD2  */
+	{GPMC_AD3 , M0 | IEN | PDIS}, /* AD3  */
+	{GPMC_AD4 , M0 | IEN | PDIS}, /* AD4  */
+	{GPMC_AD5 , M0 | IEN | PDIS}, /* AD5  */
+	{GPMC_AD6 , M0 | IEN | PDIS}, /* AD6  */
+	{GPMC_AD7 , M0 | IEN | PDIS}, /* AD7  */
+#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
+	{GPMC_AD8 , M0 | IEN | PDIS}, /* AD8  */
+	{GPMC_AD9 , M0 | IEN | PDIS}, /* AD9  */
+	{GPMC_AD10, M0 | IEN | PDIS}, /* AD10 */
+	{GPMC_AD11, M0 | IEN | PDIS}, /* AD11 */
+	{GPMC_AD12, M0 | IEN | PDIS}, /* AD12 */
+	{GPMC_AD13, M0 | IEN | PDIS}, /* AD13 */
+	{GPMC_AD14, M0 | IEN | PDIS}, /* AD14 */
+	{GPMC_AD15, M0 | IEN | PDIS}, /* AD15 */
+#endif
+	{GPMC_CS0,	M0 | IDIS | PEN | PTU}, /* chip-select */
+	{GPMC_ADVN_ALE,	M0 | IDIS | PEN | PTD}, /* Addr latch */
+	{GPMC_OEN_REN,	M0 | IDIS | PEN | PTD}, /* Read enable */
+	{GPMC_WEN,	M0 | IDIS | PEN | PTU}, /* Write enable_n */
+	{GPMC_BEN0,	M0 | IDIS | PEN | PTD}, /* Byte/Column En */
+	{GPMC_WAIT0,	M0 | IEN  | PEN | PTU}, /* Wait/Ready */
+	/* GPMC_WPN (Write Protect) is controlled by DIP Switch SW10(12) */
+#else
+	/* QSPI pin-mux */
 	{GPMC_A13, (IEN | PDIS | M1)},  /* QSPI1_RTCLK */
 	{GPMC_A14, (IEN | PDIS | M1)},  /* QSPI1_D[3] */
 	{GPMC_A15, (IEN | PDIS | M1)},  /* QSPI1_D[2] */
@@ -61,6 +90,7 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
 	{GPMC_A4, (IEN | PDIS | M1)},   /* QSPI1_CS3 */
 	{GPMC_CS2, (IEN | PTU | PDIS | M1)},    /* QSPI1_CS0 */
 	{GPMC_CS3, (IEN | PTU | PDIS | M1)},    /* QSPI1_CS1*/
+#endif /* CONFIG_NAND */
 	{USB2_DRVVBUS, (M0 | IEN | FSC) },
 };
 #endif /* _MUX_DATA_DRA7XX_H_ */
diff --git a/boards.cfg b/boards.cfg
index 52aeb7f..1cc0e94 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -361,7 +361,7 @@ Active  arm         armv7          omap4       gumstix         duovero
 Active  arm         armv7          omap4       ti              panda               omap4_panda                           -                                                                                                                                 Sricharan R <r.sricharan at ti.com>
 Active  arm         armv7          omap4       ti              sdp4430             omap4_sdp4430                         -                                                                                                                                 Sricharan R <r.sricharan at ti.com>
 Active  arm         armv7          omap5       compulab        cm_t54              cm_t54                                -                                                                                                                                 Dmitry Lifshitz <lifshitz at compulab.co.il>
-Active  arm         armv7          omap5       ti              dra7xx              dra7xx_evm                            dra7xx_evm:CONS_INDEX=1                                                                                                           Lokesh Vutla <lokeshvutla at ti.com>
+Active  arm         armv7          omap5       ti              dra7xx              dra7xx_evm                            dra7xx_evm:CONS_INDEX=1,NAND                                                                                                      Lokesh Vutla <lokeshvutla at ti.com>
 Active  arm         armv7          omap5       ti              dra7xx              dra7xx_evm_qspiboot                   dra7xx_evm:CONS_INDEX=1,QSPI_BOOT                                                                                                 Lokesh Vutla <lokeshvutla at ti.com>
 Active  arm         armv7          omap5       ti              dra7xx              dra7xx_evm_uart3                      dra7xx_evm:CONS_INDEX=3,SPL_YMODEM_SUPPORT                                                                                        Lokesh Vutla <lokeshvutla at ti.com>
 Active  arm         armv7          omap5       ti              omap5_uevm          omap5_uevm                            -                                                                                                                                 -
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 8d0a0eb..9e6a565 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -14,7 +14,7 @@
 
 #define CONFIG_DRA7XX
 
-#ifndef CONFIG_QSPI_BOOT
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_NAND)
 /* MMC ENV related defines */
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV		1	/* SLOT2: eMMC(1) */
@@ -143,4 +143,60 @@
 #define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 						CONFIG_SYS_SCSI_MAX_LUN)
 
+/* NAND support */
+#ifdef CONFIG_NAND
+/* NAND: device related configs */
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					 CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+/* NAND: driver related configs */
+#define CONFIG_SPL_NAND_AM33XX_BCH
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_NAND_OMAP_ELM
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+					 10, 11, 12, 13, 14, 15, 16, 17, \
+					 18, 19, 20, 21, 22, 23, 24, 25, \
+					 26, 27, 28, 29, 30, 31, 32, 33, \
+					 34, 35, 36, 37, 38, 39, 40, 41, \
+					 42, 43, 44, 45, 46, 47, 48, 49, \
+					 50, 51, 52, 53, 54, 55, 56, 57, }
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	14
+#define MTDIDS_DEFAULT			"nand0=nand.0"
+#define MTDPARTS_DEFAULT		"mtdparts=nand.0:" \
+					"128k(NAND.SPL)," \
+					"128k(NAND.SPL.backup1)," \
+					"128k(NAND.SPL.backup2)," \
+					"128k(NAND.SPL.backup3)," \
+					"256k(NAND.u-boot-spl-os)," \
+					"1m(NAND.u-boot)," \
+					"128k(NAND.u-boot-env)," \
+					"128k(NAND.u-boot-env.backup1)," \
+					"8m(NAND.kernel)," \
+					"-(NAND.rootfs)"
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x000c0000
+#define CONFIG_ENV_OFFSET		0x001c0000
+#define CONFIG_ENV_OFFSET_REDUND	0x001e0000
+#define CONFIG_SYS_ENV_SECT_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_SIZE			(128 * 1024)
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_NAND
+/* NAND: SPL related configs */
+#if defined(CONFIG_SPL_NAND_SUPPORT)
+  /* NAND: SPL falcon mode configs */
+  #ifdef CONFIG_SPL_OS_BOOT
+    #define CONFIG_CMD_SPL_NAND_OFS		0x00080000 /* os-boot params*/
+    #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x00200000 /* kernel offset */
+    #define CONFIG_CMD_SPL_WRITE_SIZE		0x2000
+  #endif
+#endif
+#endif /* !CONFIG_NAND */
+
 #endif /* __CONFIG_DRA7XX_EVM_H */
-- 
1.8.5.1.163.gd7aced9



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