[U-Boot] [PATCH v5 02/11] ARM: HYP/non-sec: add a barrier after setting SCR.NS==1
Ian Campbell
ijc at hellion.org.uk
Sat Jul 12 15:23:59 CEST 2014
From: Marc Zyngier <marc.zyngier at arm.com>
A CP15 instruction execution can be reordered, requiring an
isb to be sure it is executed in program order.
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
Acked-by: Ian Campbell <ijc at hellion.org.uk>
---
arch/arm/cpu/armv7/nonsec_virt.S | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
index 6367e09..12de5c2 100644
--- a/arch/arm/cpu/armv7/nonsec_virt.S
+++ b/arch/arm/cpu/armv7/nonsec_virt.S
@@ -46,6 +46,7 @@ _secure_monitor:
#endif
mcr p15, 0, r1, c1, c1, 0 @ write SCR (with NS bit set)
+ isb
#ifdef CONFIG_ARMV7_VIRT
mrceq p15, 0, r0, c12, c0, 1 @ get MVBAR value
--
2.0.1
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