[U-Boot] [PATCH v2 5/5] arm, imx6: add aristainetos board
Stefano Babic
sbabic at denx.de
Tue Jul 15 10:31:36 CEST 2014
Hi Heiko,
On 12/07/2014 06:10, Heiko Schocher wrote:
> CPU: Freescale i.MX6DL rev1.1 at 792 MHz
> Board: aristaitenos
> I2C: ready
> DRAM: 1 GiB
> NAND: 512 MiB
> MMC: FSL_SDHC: 0, FSL_SDHC: 1
> SF: Detected N25Q128 with page size 256 Bytes, erase size 64 KiB, total 16 MiB
> Display: lb07wv8 (800x480)
>
> - UART5 is console
> - MMC 0 and 1
> - USB 0 and 1
> - boot from mmc0 and spi nor flash
> - Splash screen support
>
> Signed-off-by: Heiko Schocher <hs at denx.de>
> Cc: Stefano Babic <sbabic at denx.de>
>
> ---
> - changes for v2:
> - change MUX_PAD_CTRL value for MX6_PAD_GPIO_16__ENET_REF_CLK
> - set cs1 from ecspi4 to high
> - add splash screen support
> - add comment from Stefano babic:
> - remove mxc_iomux_set_gpr_register instead use setbits_le32
> remove patch http://patchwork.ozlabs.org/patch/353324/
> from this patchserie, as no longer needed
> - use for loop for calling enable_spi_clk()
> - simplify board_mmc_getcd()
> - simplify board_mmc_init()
> - remove board_phy_config()
> - remove setup_fec() and work code into
> board_eth_init()
> - use define for i2c slave address
> - remove udelay in board_ehci_hcd_init()
> - remove CONFIG_SPL_BUILD, as this board does not use
> CONFIG_SPL_BUILD
>
> board/aristainetos/Makefile | 9 +
> board/aristainetos/aristainetos.c | 632 ++++++++++++++++++++++++++++++++++++
> board/aristainetos/aristainetos.cfg | 33 ++
> board/aristainetos/clocks.cfg | 24 ++
> board/aristainetos/ddr-setup.cfg | 61 ++++
> board/aristainetos/mt41j128M.cfg | 70 ++++
> boards.cfg | 1 +
> include/configs/aristainetos.h | 330 +++++++++++++++++++
> 8 files changed, 1160 insertions(+)
> create mode 100644 board/aristainetos/Makefile
> create mode 100644 board/aristainetos/aristainetos.c
> create mode 100644 board/aristainetos/aristainetos.cfg
> create mode 100644 board/aristainetos/clocks.cfg
> create mode 100644 board/aristainetos/ddr-setup.cfg
> create mode 100644 board/aristainetos/mt41j128M.cfg
> create mode 100644 include/configs/aristainetos.h
>
> diff --git a/board/aristainetos/Makefile b/board/aristainetos/Makefile
> new file mode 100644
> index 0000000..5de48bc
> --- /dev/null
> +++ b/board/aristainetos/Makefile
> @@ -0,0 +1,9 @@
> +#
> +# Copyright (C) 2007, Guennadi Liakhovetski <lg at denx.de>
> +#
> +# (C) Copyright 2011 Freescale Semiconductor, Inc.
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +obj-y := aristainetos.o
> diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c
> new file mode 100644
> index 0000000..7a61033
> --- /dev/null
> +++ b/board/aristainetos/aristainetos.c
> @@ -0,0 +1,632 @@
> +/*
> + * (C) Copyright 2014
> + * Heiko Schocher, DENX Software Engineering, hs at denx.de.
> + *
> + * Based on:
> + * Copyright (C) 2012 Freescale Semiconductor, Inc.
> + *
> + * Author: Fabio Estevam <fabio.estevam at freescale.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <asm/arch/clock.h>
> +#include <asm/arch/imx-regs.h>
> +#include <asm/arch/iomux.h>
> +#include <asm/arch/mx6-pins.h>
> +#include <asm/errno.h>
> +#include <asm/gpio.h>
> +#include <asm/imx-common/iomux-v3.h>
> +#include <asm/imx-common/boot_mode.h>
> +#include <asm/imx-common/mxc_i2c.h>
> +#include <asm/imx-common/video.h>
> +#include <mmc.h>
> +#include <fsl_esdhc.h>
> +#include <miiphy.h>
> +#include <netdev.h>
> +#include <asm/arch/mxc_hdmi.h>
> +#include <asm/arch/crm_regs.h>
> +#include <linux/fb.h>
> +#include <ipu_pixfmt.h>
> +#include <asm/io.h>
> +#include <asm/arch/sys_proto.h>
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
> + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
> + PAD_CTL_SRE_FAST | PAD_CTL_HYS)
> +
> +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
> + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
> + PAD_CTL_SRE_FAST | PAD_CTL_HYS)
> +
> +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
> + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
> +
> +#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
> + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
> +
> +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
> + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
> + PAD_CTL_ODE | PAD_CTL_SRE_FAST)
> +
> +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
> +
> +#define DISP_PAD_CTRL (0x10)
> +
> +#define ECSPI4_CS1 IMX_GPIO_NR(5, 2)
> +
> +struct i2c_pads_info i2c_pad_info1 = {
> + .scl = {
> + .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
> + .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
> + .gp = IMX_GPIO_NR(5, 27)
> + },
> + .sda = {
> + .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
> + .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
> + .gp = IMX_GPIO_NR(5, 26)
> + }
> +};
> +
> +struct i2c_pads_info i2c_pad_info2 = {
> + .scl = {
> + .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
> + .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
> + .gp = IMX_GPIO_NR(4, 12)
> + },
> + .sda = {
> + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
> + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
> + .gp = IMX_GPIO_NR(4, 13)
> + }
> +};
> +
> +struct i2c_pads_info i2c_pad_info3 = {
> + .scl = {
> + .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
> + .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
> + .gp = IMX_GPIO_NR(3, 17)
> + },
> + .sda = {
> + .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
> + .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
> + .gp = IMX_GPIO_NR(3, 18)
> + }
> +};
> +
> +int dram_init(void)
> +{
> + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
> +
> + return 0;
> +}
> +
> +iomux_v3_cfg_t const uart1_pads[] = {
> + MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
> + MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
> +};
> +
> +iomux_v3_cfg_t const uart5_pads[] = {
> + MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
> + MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
> +};
> +
> +iomux_v3_cfg_t const gpio_pads[] = {
> + /* LED enable */
> + MX6_PAD_SD4_DAT5__GPIO2_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + /* spi flash WP protect */
> + MX6_PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + /* backlight enable */
> + MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + /* LED yellow */
> + MX6_PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + /* LED red */
> + MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + /* LED green */
> + MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + /* LED blue */
> + MX6_PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + /* i2c4 scl */
> + MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + /* i2c4 sda */
> + MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + /* spi CS 1 */
> + MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +static iomux_v3_cfg_t const misc_pads[] = {
> + MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
> + /* OTG Power enable */
> + MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +iomux_v3_cfg_t const enet_pads[] = {
> + MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(0x4001b0a8),
> + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +};
> +
> +static void setup_iomux_enet(void)
> +{
> + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
> +
> + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
> +
> + /* set GPIO_16 as ENET_REF_CLK_OUT */
> + setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
> +}
> +
> +iomux_v3_cfg_t const usdhc1_pads[] = {
> + MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +};
> +
> +iomux_v3_cfg_t const usdhc2_pads[] = {
> + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +};
> +
> +iomux_v3_cfg_t const ecspi4_pads[] = {
> + MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +static iomux_v3_cfg_t const display_pads[] = {
> + MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL),
> + MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
> + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
> + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
> + MX6_PAD_DI0_PIN4__GPIO4_IO20,
> + MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
> + MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
> + MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
> + MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
> + MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
> + MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
> + MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
> + MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
> + MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
> + MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
> + MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
> + MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
> + MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
> + MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
> + MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
> + MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
> + MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
> + MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
> + MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
> + MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
> + MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
> + MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
> + MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
> + MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
> +};
> +
> +static iomux_v3_cfg_t const backlight_pads[] = {
> + MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_SD4_DAT1__PWM3_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +static void setup_spi(void)
> +{
> + int i;
> +
> + imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads));
> + for (i = 0; i < 3; i++)
> + enable_spi_clk(true, i);
> +
> + /* set cs1 to high */
> + gpio_direction_output(ECSPI4_CS1, 1);
> +}
> +
> +static void setup_iomux_gpio(void)
> +{
> + imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
> +}
> +
> +static void setup_iomux_uart(void)
> +{
> + if (CONFIG_MXC_UART_BASE == UART1_BASE)
> + imx_iomux_v3_setup_multiple_pads(uart1_pads,
> + ARRAY_SIZE(uart1_pads));
> + else
> + imx_iomux_v3_setup_multiple_pads(uart5_pads,
> + ARRAY_SIZE(uart5_pads));
> +}
Why do you check this ? You explained that console is on uart5. Either
you use uart1, too, or you dropped it becase the condition is never
verified.
> +
> +#ifdef CONFIG_FSL_ESDHC
> +struct fsl_esdhc_cfg usdhc_cfg[2] = {
> + {USDHC1_BASE_ADDR},
> + {USDHC2_BASE_ADDR},
> +};
> +
> +int board_mmc_getcd(struct mmc *mmc)
> +{
> + return 1;
> +}
> +
> +int board_mmc_init(bd_t *bis)
> +{
> + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
> + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
> +
> + imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
> + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
> +
> + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]) |
> + fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
> +}
> +#endif
> +
> +/*
> + * Do not overwrite the console
> + * Use always serial for U-Boot console
> + */
> +int overwrite_console(void)
> +{
> + return 1;
> +}
> +
> +int board_eth_init(bd_t *bis)
> +{
> + struct iomuxc_base_regs *iomuxc_regs =
> + (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
> + int ret;
> +
> + setup_iomux_enet();
> + /* clear gpr1[14], gpr1[18:17] to select anatop clock */
> + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
> +
> + ret = enable_fec_anatop_clock(ENET_50MHz);
> + if (ret)
> + return ret;
> +
> + return cpu_eth_init(bis);
> +}
> +#if defined(CONFIG_VIDEO_IPUV3)
> +
> +static void enable_lvds(struct display_info_t const *dev)
> +{
> + struct pwm_regs *pwm = (struct pwm_regs *)PWM3_BASE_ADDR;
> +
> + imx_iomux_v3_setup_multiple_pads(
> + display_pads,
> + ARRAY_SIZE(display_pads));
> + imx_iomux_v3_setup_multiple_pads(
> + backlight_pads,
> + ARRAY_SIZE(backlight_pads));
> +
> + /* enable backlight PWM 3 */
> + writel(PWMCR_EN | PWMCR_CLKSRC_IPG_HIGH | PWMCR_DBGEN |
> + PWMCR_WAITEN | PWMCR_DOZEEN, &pwm->cr);
> + writel(0, &pwm->ir);
> + /* set duty cycles */
> + writel(0x20, &pwm->sar);
> + /* set period cycles */
> + writel(0xc4, &pwm->pr);
See my comment for previous patch regarding PWM registers.
> +}
> +
> +static void enable_spi(struct display_info_t const *dev)
> +{
> + return;
> +};
This is statis and does nothing. Can we drop it ?
> +
> +struct display_info_t const displays[] = {{
> + .bus = -1,
> + .addr = 0,
> + .pixfmt = IPU_PIX_FMT_RGB24,
> + .detect = NULL,
> + .enable = enable_lvds,
> + .mode = {
> + .name = "lb07wv8",
> + .refresh = 60,
> + .xres = 800,
> + .yres = 480,
> + .pixclock = 33246,
> + .left_margin = 88,
> + .right_margin = 88,
> + .upper_margin = 10,
> + .lower_margin = 10,
> + .hsync_len = 25,
> + .vsync_len = 1,
> + .sync = 0,
> + .vmode = FB_VMODE_NONINTERLACED
> +} }, {
> + .bus = -1,
> + .addr = 0,
> + .pixfmt = IPU_PIX_FMT_RGB24,
> + .detect = NULL,
> + .enable = enable_spi,
> + .mode = {
> + .name = "lg4573",
> + .refresh = 60,
> + .xres = 480,
> + .yres = 800,
> + .pixclock = 30000,
> + .left_margin = 59,
> + .right_margin = 10,
> + .upper_margin = 15,
> + .lower_margin = 15,
> + .hsync_len = 10,
> + .vsync_len = 15,
> + .sync = 0,
> + .vmode = FB_VMODE_NONINTERLACED
> +} } };
> +size_t display_count = ARRAY_SIZE(displays);
> +
> +static void setup_display(void)
> +{
> + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> + int reg;
> +
> + enable_ipu_clock();
> +
> + reg = readl(&mxc_ccm->cs2cdr);
> + /* select pll 5 clock */
> + reg &= MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK;
> + reg &= MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK;
> + writel(reg, &mxc_ccm->cs2cdr);
> +
> + imx_iomux_v3_setup_multiple_pads(backlight_pads,
> + ARRAY_SIZE(backlight_pads));
> +}
> +
> +/* no console on this board */
> +int board_cfb_skip(void)
> +{
> + return 1;
> +}
> +#endif
> +
> +int board_early_init_f(void)
> +{
> + setup_iomux_uart();
> + setup_iomux_gpio();
> +
> +#if defined(CONFIG_VIDEO_IPUV3)
> + setup_display();
> +#endif
> + return 0;
> +}
> +
> +iomux_v3_cfg_t nfc_pads[] = {
> + MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +static void setup_gpmi_nand(void)
> +{
> + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> +
> + /* config gpmi nand iomux */
> + imx_iomux_v3_setup_multiple_pads(nfc_pads,
> + ARRAY_SIZE(nfc_pads));
> +
> + /* config gpmi and bch clock to 100 MHz */
> + clrsetbits_le32(&mxc_ccm->cs2cdr,
> + MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
> + MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
> + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
> + MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
> + MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
> + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
> +
> + /* enable gpmi and bch clock gating */
> + setbits_le32(&mxc_ccm->CCGR4,
> + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
> + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
> + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
> + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
> + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
> +
> + /* enable apbh clock gating */
> + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
> +}
> +
> +#include <spi.h>
Why is the include here ?
> +static void spi_read(struct spi_slave *spi)
> +{
> + int ret;
> + unsigned long flags = SPI_XFER_BEGIN;
> + int cmd_len;
> + u8 cmd[2];
> + u8 val;
> +
> + if (!spi)
> + return;
> +
> + cmd[0] = 0x05;
> + cmd_len = 1;
> + ret = spi_xfer(spi, cmd_len * 8, cmd, &val, flags);
> + if (ret) {
> + debug("Failed to send command (%zu bytes): %d\n",
> + cmd_len, ret);
> + return;
> + }
> + flags |= SPI_XFER_END;
> + val = 0;
> + cmd_len = 1;
> + ret = spi_xfer(spi, cmd_len * 8, NULL, &val, flags);
> + if (ret) {
> + debug("Failed to read (%zu bytes): %d\n",
> + cmd_len, ret);
> + return;
> + }
> +}
> +
> +static void spi_write(struct spi_slave *spi, u8 reg, u8 val, int len)
> +{
> + int ret;
> + unsigned long flags = SPI_XFER_BEGIN;
> + int cmd_len;
> + u8 cmd[2];
> +
> + if (!spi)
> + return;
> +
> + flags |= SPI_XFER_END;
> + cmd[0] = reg;
> + cmd[1] = val;
> + cmd_len = len;
> + ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags);
> + if (ret) {
> + debug("Failed to send command (%zu bytes): %d\n",
> + cmd_len, ret);
> + }
> +}
> +
> +static void spi_enable_wp(void)
> +{
> + struct spi_slave *spi;
> + int ret;
> +
> + spi = spi_setup_slave(CONFIG_SF_DEFAULT_BUS, CONFIG_SF_DEFAULT_CS,
> + CONFIG_SF_DEFAULT_SPEED,
> + CONFIG_SF_DEFAULT_MODE);
> + if (!spi) {
> + printf("Failed to set up slave\n");
> + return;
> + }
> +
> + ret = spi_claim_bus(spi);
> + if (ret) {
> + debug("Failed to claim SPI bus: %d\n", ret);
> + goto err_claim_bus;
> + }
> +
> + spi_read(spi);
> + spi_write(spi, 0x06, 0x80, 1);
> + spi_write(spi, 0x01, 0x80, 2);
> + spi_read(spi);
> + spi_read(spi);
> + spi_write(spi, 0x04, 0x80, 1);
> + spi_read(spi);
> +
> + spi_release_bus(spi);
> +err_claim_bus:
> + spi_free_slave(spi);
> +}
The three SPI functions are quite cryptic. If they are for a SPI eprom,
the code should go into drivers/mtd/spi, but not directly into board code.
> +
> +int board_init(void)
> +{
> + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
> +
> + /* address of boot parameters */
> + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
> +
> + setup_spi();
> +
> + setup_i2c(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
> + &i2c_pad_info1);
> + setup_i2c(1, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
> + &i2c_pad_info2);
> + setup_i2c(2, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
> + &i2c_pad_info3);
> +
> + /* i2c4 not used, set it to gpio input */
> + gpio_request(IMX_GPIO_NR(1, 7), "i2c4_scl");
> + gpio_direction_input(IMX_GPIO_NR(1, 7));
> + gpio_request(IMX_GPIO_NR(1, 8), "i2c4_sda");
> + gpio_direction_input(IMX_GPIO_NR(1, 8));
> +
> + /* SPI NOR Flash read only */
> + gpio_request(CONFIG_GPIO_ENABLE_SPI_FLASH, "ena_spi_nor");
> + gpio_direction_output(CONFIG_GPIO_ENABLE_SPI_FLASH, 0);
> + gpio_free(CONFIG_GPIO_ENABLE_SPI_FLASH);
> +
> + /* enable LED */
> + gpio_request(IMX_GPIO_NR(2, 13), "LED ena");
> + gpio_direction_output(IMX_GPIO_NR(2, 13), 0);
> +
> + gpio_request(IMX_GPIO_NR(1, 3), "LED yellow");
> + gpio_direction_output(IMX_GPIO_NR(1, 3), 1);
> + gpio_request(IMX_GPIO_NR(1, 4), "LED red");
> + gpio_direction_output(IMX_GPIO_NR(1, 4), 1);
> + gpio_request(IMX_GPIO_NR(1, 5), "LED green");
> + gpio_direction_output(IMX_GPIO_NR(1, 5), 1);
> + gpio_request(IMX_GPIO_NR(1, 6), "LED blue");
> + gpio_direction_output(IMX_GPIO_NR(1, 6), 1);
> +
> + setup_gpmi_nand();
> +
> + /* GPIO_1 for USB_OTG_ID */
> + setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK);
> + imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
> +
> + return 0;
> +}
> +
> +int board_late_init(void)
> +{
> + spi_enable_wp();
> +
> + return 0;
> +}
> +
> +int checkboard(void)
> +{
> + puts("Board: aristaitenos\n");
> + return 0;
> +}
> +
> +#ifdef CONFIG_USB_EHCI_MX6
> +int board_ehci_hcd_init(int port)
> +{
> + int ret;
> +
> + ret = gpio_request(ARISTAINETOS_USB_H1_PWR, "usb-h1-pwr");
> + if (!ret)
> + gpio_direction_output(ARISTAINETOS_USB_H1_PWR, 1);
> + ret = gpio_request(ARISTAINETOS_USB_OTG_PWR, "usb-OTG-pwr");
> + if (!ret)
> + gpio_direction_output(ARISTAINETOS_USB_OTG_PWR, 1);
> + return 0;
> +}
> +
> +int board_ehci_power(int port, int on)
> +{
> + if (port)
> + gpio_set_value(ARISTAINETOS_USB_OTG_PWR, on);
> + else
> + gpio_set_value(ARISTAINETOS_USB_H1_PWR, on);
> + return 0;
> +}
> +#endif
> diff --git a/board/aristainetos/aristainetos.cfg b/board/aristainetos/aristainetos.cfg
> new file mode 100644
> index 0000000..2290180
> --- /dev/null
> +++ b/board/aristainetos/aristainetos.cfg
> @@ -0,0 +1,33 @@
> +/*
> + * (C) Copyright 2014
> + * Heiko Schocher, DENX Software Engineering, hs at denx.de.
> + *
> + * Based on:
> + * Copyright (C) 2013 Boundary Devices
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + *
> + * Refer doc/README.imximage for more details about how-to configure
> + * and create imximage boot image
> + *
> + * The syntax is taken as close as possible with the kwbimage
> + */
> +
> +/* image version */
> +IMAGE_VERSION 2
> +
> +/*
> + * Boot Device : one of
> + * spi, sd
> + */
> +BOOT_FROM spi
> +
> +#define __ASSEMBLY__
> +#include <config.h>
> +#include "asm/arch/mx6-ddr.h"
> +#include "asm/arch/iomux.h"
> +#include "asm/arch/crm_regs.h"
> +
> +#include "ddr-setup.cfg"
> +#include "mt41j128M.cfg"
> +#include "clocks.cfg"
> diff --git a/board/aristainetos/clocks.cfg b/board/aristainetos/clocks.cfg
> new file mode 100644
> index 0000000..651449e
> --- /dev/null
> +++ b/board/aristainetos/clocks.cfg
> @@ -0,0 +1,24 @@
> +/*
> + * Copyright (C) 2013 Boundary Devices
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + *
> + * Device Configuration Data (DCD)
> + *
> + * Each entry must have the format:
> + * Addr-type Address Value
> + *
> + * where:
> + * Addr-type register length (1,2 or 4 bytes)
> + * Address absolute address of the register
> + * value value to be stored in the register
> + */
> +
> +/* set the default clock gate to save power */
> +DATA 4, CCM_CCGR0, 0x00c03f3f
> +DATA 4, CCM_CCGR1, 0x0030fcff
> +DATA 4, CCM_CCGR2, 0x0fffcfc0
> +DATA 4, CCM_CCGR3, 0x3ff0300f
> +DATA 4, CCM_CCGR4, 0xfffff30c /* enable NAND/GPMI/BCH clocks */
> +DATA 4, CCM_CCGR5, 0x0f0000c3
> +DATA 4, CCM_CCGR6, 0x000003ff
> diff --git a/board/aristainetos/ddr-setup.cfg b/board/aristainetos/ddr-setup.cfg
> new file mode 100644
> index 0000000..c72a3ef
> --- /dev/null
> +++ b/board/aristainetos/ddr-setup.cfg
> @@ -0,0 +1,61 @@
> +/*
> + * Copyright (C) 2013 Boundary Devices
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + *
> + * Device Configuration Data (DCD)
> + *
> + * Each entry must have the format:
> + * Addr-type Address Value
> + *
> + * where:
> + * Addr-type register length (1,2 or 4 bytes)
> + * Address absolute address of the register
> + * value value to be stored in the register
> + */
> +
> +/* DDR IO TYPE */
> +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
> +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
> +/* Clock */
> +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030
> +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030
> +/* Address */
> +DATA 4, MX6_IOM_DRAM_CAS, 0x00000030
> +DATA 4, MX6_IOM_DRAM_RAS, 0x00000030
> +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
> +/* Control */
> +DATA 4, MX6_IOM_DRAM_RESET, 0x00000030
> +DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
> +DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
> +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
> +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
> +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
> +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
> +/* Data Strobe */
> +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
> +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
> +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
> +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
> +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
> +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
> +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
> +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
> +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
> +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
> +DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
> +DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
> +DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
> +DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
> +DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
> +DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
> +DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
> +DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
> +DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030
> +DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030
> +DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030
> +DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030
> +DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030
> +DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030
> +DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030
> +DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030
> diff --git a/board/aristainetos/mt41j128M.cfg b/board/aristainetos/mt41j128M.cfg
> new file mode 100644
> index 0000000..3561655
> --- /dev/null
> +++ b/board/aristainetos/mt41j128M.cfg
> @@ -0,0 +1,70 @@
> +/*
> + * Copyright (C) 2013 Boundary Devices
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +/* ZQ Calibration */
> +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
> +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xa1390003
> +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
> +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
> +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F
> +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F
> +/*
> + * DQS gating, read delay, write delay calibration values
> + * based on calibration compare of 0x00ffff00
> + */
> +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x420E020E
> +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02000200
> +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42020202
> +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x01720172
> +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x494C4F4C
> +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4A4C4C49
> +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3133
> +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x39373F2E
> +/* read data bit delay */
> +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
> +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
> +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
> +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
> +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
> +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
> +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
> +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
> +/* Complete calibration by forced measurment */
> +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
> +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
> +/* in DDR3, 64-bit mode, only MMDC0 is initiated */
> +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002d
> +DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
> +DATA 4, MX6_MMDC_P0_MDCFG0, 0x40445323
> +DATA 4, MX6_MMDC_P0_MDCFG1, 0xb66e8c63
> +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db
> +DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
> +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
> +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2
> +DATA 4, MX6_MMDC_P0_MDOR, 0x00440e21
> +DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
> +DATA 4, MX6_MMDC_P0_MDCTL, 0x84190000
> +/* MR2 */
> +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
> +DATA 4, MX6_MMDC_P0_MDSCR, 0x0400803a
> +/* MR3 */
> +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
> +DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803b
> +/* MR1 */
> +DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
> +DATA 4, MX6_MMDC_P0_MDSCR, 0x00428039
> +/* MR0 */
> +DATA 4, MX6_MMDC_P0_MDSCR, 0x07208030
> +DATA 4, MX6_MMDC_P0_MDSCR, 0x07208038
> +/* ZQ calibration */
> +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
> +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048
> +/* final ddr setup */
> +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
> +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007
> +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000007
> +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556d
> +DATA 4, MX6_MMDC_P1_MAPSR, 0x00011006
> +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
> diff --git a/boards.cfg b/boards.cfg
> index f16a0e6..348d68d 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -311,6 +311,7 @@ Active arm armv7 mx5 freescale mx53smd
> Active arm armv7 mx5 genesi mx51_efikamx mx51_efikamx mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg -
> Active arm armv7 mx5 genesi mx51_efikamx mx51_efikasb mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg -
> Active arm armv7 mx5 ttcontrol vision2 vision2 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg Stefano Babic <sbabic at denx.de>
> +Active arm armv7 mx6 - aristainetos aristainetos aristainetos:IMX_CONFIG=board/aristainetos/aristainetos.cfg,MX6DL Heiko Schocher <hs at denx.de>
> Active arm armv7 mx6 - udoo udoo_quad udoo:IMX_CONFIG=board/udoo/udoo.cfg,MX6Q,DDR_MB=1024 Fabio Estevam <fabio.estevam at freescale.com>
> Active arm armv7 mx6 - wandboard wandboard_dl wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 Fabio Estevam <fabio.estevam at freescale.com>
> Active arm armv7 mx6 - wandboard wandboard_quad wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 Fabio Estevam <fabio.estevam at freescale.com>
> diff --git a/include/configs/aristainetos.h b/include/configs/aristainetos.h
> new file mode 100644
> index 0000000..d2025e1
> --- /dev/null
> +++ b/include/configs/aristainetos.h
> @@ -0,0 +1,330 @@
> +/*
> + * (C) Copyright 2014
> + * Heiko Schocher, DENX Software Engineering, hs at denx.de.
> + *
> + * Based on:
> + * Copyright (C) 2012 Freescale Semiconductor, Inc.
> + *
> + * Configuration settings for the Freescale i.MX6Q SabreSD board.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +#ifndef __ARISTAINETOS_CONFIG_H
> +#define __ARISTAINETOS_CONFIG_H
> +
> +#define CONFIG_MX6
> +
> +#include "mx6_common.h"
> +#include <linux/sizes.h>
> +
> +#define CONFIG_DISPLAY_CPUINFO
> +#define CONFIG_DISPLAY_BOARDINFO
> +
> +#include <asm/arch/imx-regs.h>
> +#include <asm/imx-common/gpio.h>
> +
> +#define CONFIG_MACH_TYPE 4501
> +#define CONFIG_MMCROOT "/dev/mmcblk0p2"
> +#define CONFIG_DEFAULT_FDT_FILE "aristainetos.dtb"
> +#define CONFIG_HOSTNAME aristainetos
> +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
> +
> +#define CONFIG_SYS_GENERIC_BOARD
> +
> +/* Size of malloc() pool */
> +#define CONFIG_SYS_MALLOC_LEN (64 * SZ_1M)
> +
> +#define CONFIG_BOARD_EARLY_INIT_F
> +#define CONFIG_BOARD_LATE_INIT
> +#define CONFIG_MXC_GPIO
> +
> +#define CONFIG_MXC_UART
> +#define CONFIG_MXC_UART_BASE UART5_BASE
> +#define CONFIG_CONSOLE_DEV "ttymxc4"
> +
> +#define CONFIG_CMD_FUSE
> +#ifdef CONFIG_CMD_FUSE
> +#define CONFIG_MXC_OCOTP
> +#endif
> +
> +/* MMC Configs */
> +#define CONFIG_FSL_ESDHC
> +#define CONFIG_FSL_USDHC
> +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
> +
> +#define CONFIG_MMC
> +#define CONFIG_CMD_MMC
> +#define CONFIG_GENERIC_MMC
> +#define CONFIG_BOUNCE_BUFFER
> +#define CONFIG_CMD_EXT2
> +#define CONFIG_CMD_FAT
> +#define CONFIG_DOS_PARTITION
> +
> +#define CONFIG_CMD_PING
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_MII
> +#define CONFIG_CMD_NET
> +#define CONFIG_FEC_MXC
> +#define CONFIG_MII
> +#define IMX_FEC_BASE ENET_BASE_ADDR
> +#define CONFIG_FEC_XCV_TYPE RMII
> +#define CONFIG_ETHPRIME "FEC"
> +#define CONFIG_FEC_MXC_PHYADDR 0
> +
> +#define CONFIG_PHYLIB
> +#define CONFIG_PHY_MICREL
> +
> +#define CONFIG_CMD_SF
> +#ifdef CONFIG_CMD_SF
> +#define CONFIG_SPI_FLASH
> +#define CONFIG_SPI_FLASH_MTD
> +#define CONFIG_SPI_FLASH_STMICRO
> +#define CONFIG_MXC_SPI
> +#define CONFIG_SF_DEFAULT_BUS 3
> +#define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(3, 20)<<8))
> +#define CONFIG_SF_DEFAULT_SPEED 20000000
> +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
> +#endif
> +
> +/* allow to overwrite serial and ethaddr */
> +#define CONFIG_ENV_OVERWRITE
> +#define CONFIG_CONS_INDEX 1
> +#define CONFIG_BAUDRATE 115200
> +
> +/* Command definition */
> +#include <config_cmd_default.h>
> +
> +#define CONFIG_CMD_BMODE
> +#define CONFIG_CMD_BOOTZ
> +#define CONFIG_CMD_SETEXPR
> +#undef CONFIG_CMD_IMLS
> +
> +#define CONFIG_BOOTDELAY 3
> +
> +#define CONFIG_LOADADDR 0x12000000
> +#define CONFIG_SYS_TEXT_BASE 0x17800000
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "uimage=uImage\0" \
> + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
> + "fdt_addr_r=0x11000000\0" \
> + "kernel_addr_r=0x12000000\0" \
> + "kernel_file=uImage\0" \
> + "boot_fdt=try\0" \
> + "ip_dyn=yes\0" \
> + "console=" CONFIG_CONSOLE_DEV "\0" \
> + "fdt_high=0xffffffff\0" \
> + "initrd_high=0xffffffff\0" \
> + "mmcpart=1\0" \
> + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
> + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
> + "mmcargs=setenv bootargs console=${console},${baudrate} " \
> + "root=${mmcroot}\0" \
> + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${kernel_addr_r} " \
> + "${uimage}\0" \
> + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} " \
> + "${fdt_file}\0" \
> + "mmcboot=echo Booting from mmc ...; " \
> + "run mmcargs;run loadimage loadfdt fdt_setup;" \
> + "bootm ${kernel_addr_r} - ${fdt_addr_r};\0" \
> + "rootpath=/opt/eldk-5.5/armv7a-hf/rootfs-sato-sdk\0" \
> + "nfsopts=nfsvers=3 nolock rw\0" \
> + "netdev=eth0\0" \
> + "fdt_setup=fdt addr ${fdt_addr_r};fdt resize;fdt chosen;fdt board\0"\
> + "load_fdt=tftp ${fdt_addr_r} ${fdt_file}\0" \
> + "load_kernel=tftp ${kernel_addr_r} ${kernel_file}\0" \
> + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
> + "get_env=mw ${loadaddr} 0x00000000 0x20000;" \
> + "tftp ${loadaddr} /tftpboot/aristainetos/env.txt;" \
> + "env import -t ${loadaddr}\0" \
> + "addmisc=setenv bootargs ${bootargs} maxcpus=1 loglevel=8\0" \
> + "bootargs_defaults=setenv bootargs ${console} ${mtdoops} " \
> + "${optargs}\0" \
> + "net_args=run bootargs_defaults;setenv bootargs ${bootargs} " \
> + "root=/dev/nfs nfsroot=${serverip}:${rootpath},${nfsopts} " \
> + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
> + "${hostname}:${netdev}:off\0" \
> + "net_nfs=run load_kernel load_fdt;run net_args addmtd addmisc;" \
> + "run fdt_setup;bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
> + "uboot=/tftpboot/aristainetos/u-boot.imx\0" \
> + "load_uboot=tftp ${loadaddr} ${uboot}\0" \
> + "uboot_sz=c0000\0" \
> + "upd_uboot=mw.b ${loadaddr} 0xff ${uboot_sz};" \
> + "mw.b 10200000 0x00 ${uboot_sz};" \
> + "run load_uboot;sf probe;sf erase 0 ${uboot_sz};" \
> + "sf write ${loadaddr} 400 ${filesize};" \
> + "sf read 10200000 400 ${uboot_sz};" \
> + "cmp.b ${loadaddr} 10200000 bc000\0" \
> + "ubi_prep=ubi part ubi 2048;ubifsmount ubi:kernel\0" \
> + "load_kernel_ubi=ubifsload ${kernel_addr_r} uImage\0" \
> + "load_fdt_ubi=ubifsload ${fdt_addr_r} aristainetos.dtb\0" \
> + "ubi_nfs=run ubiprep load_kernel_ubi load_fdt_ubi;" \
> + "run net_args addmtd addmisc;run fdt_setup;" \
> + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
> + "rootfsname=rootfs\0" \
> + "ubi_args=run bootargs_defaults;setenv bootargs ${bootargs} " \
> + "ubi.mtd=0,2048 root=ubi0:${rootfsname} rootfstype=ubifs " \
> + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
> + "${hostname}:${netdev}:off\0" \
> + "ubi_ubi=run ubi_prep load_kernel_ubi load_fdt_ubi;" \
> + "run bootargs_defaults ubi_args addmtd addmisc;" \
> + "run fdt_setup;bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
> + "ubirootfs_file=/tftpboot/aristainetos/rootfs-minimal.ubifs\0" \
> + "upd_ubirootfs=run ubi_prep;tftp ${loadaddr} ${ubirootfs_file};" \
> + "ubi write ${loadaddr} rootfs ${filesize}\0" \
> + "ksz=800000\0" \
> + "rootsz=2000000\0" \
> + "usersz=8000000\0" \
> + "ubi_make=run ubi_prep;ubi create kernel ${ksz};" \
> + "ubi create rootfs ${rootsz};ubi create userfs ${usersz}\0"
> +
> +#define CONFIG_BOOTCOMMAND \
> + "mmc dev ${mmcdev};" \
> + "if mmc rescan; then " \
> + "run mmcboot;" \
> + "else run ubi_ubi; fi"
> +
> +#define CONFIG_ARP_TIMEOUT 200UL
> +
> +/* Miscellaneous configurable options */
> +#define CONFIG_SYS_LONGHELP
> +#define CONFIG_SYS_HUSH_PARSER
> +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
> +#define CONFIG_AUTO_COMPLETE
> +#define CONFIG_SYS_CBSIZE 256
> +
> +/* Print Buffer Size */
> +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
> +#define CONFIG_SYS_MAXARGS 16
> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> +
> +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
> +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
> +#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
> +
> +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
> +
> +#define CONFIG_CMDLINE_EDITING
> +#define CONFIG_STACKSIZE (128 * 1024)
> +
> +/* Physical Memory Map */
> +#define CONFIG_NR_DRAM_BANKS 1
> +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
> +
> +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
> +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
> +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
> +
> +#define CONFIG_SYS_INIT_SP_OFFSET \
> + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> +#define CONFIG_SYS_INIT_SP_ADDR \
> + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> +
> +/* FLASH and environment organization */
> +#define CONFIG_SYS_NO_FLASH
> +
> +#define CONFIG_ENV_SIZE (12 * 1024)
> +#define CONFIG_ENV_IS_IN_SPI_FLASH
> +#if defined(CONFIG_ENV_IS_IN_SPI_FLASH)
> +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
> +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
> +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
> +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
> +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
> +#define CONFIG_ENV_SECT_SIZE (0x010000)
> +#define CONFIG_ENV_OFFSET (0x0c0000)
> +#define CONFIG_ENV_OFFSET_REDUND (0x0d0000)
Usually we set define for this, such as
CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
> +#endif
> +
> +#define CONFIG_OF_LIBFDT
> +
> +#ifndef CONFIG_SYS_DCACHE_OFF
> +#define CONFIG_CMD_CACHE
> +#endif
> +
> +#define CONFIG_SYS_FSL_USDHC_NUM 2
> +
> +#define CONFIG_CMD_I2C
> +#define CONFIG_SYS_I2C
> +#define CONFIG_SYS_I2C_MXC
> +#define CONFIG_SYS_I2C_SPEED 100000
> +#define CONFIG_SYS_I2C_SLAVE 0x7f
> +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x00} }
> +
> +#define CONFIG_CMD_GPIO
> +#define CONFIG_GPIO_ENABLE_SPI_FLASH IMX_GPIO_NR(2, 15)
> +
> +/* NAND stuff */
> +#define CONFIG_CMD_NAND
> +#define CONFIG_CMD_NAND_TRIMFFS
> +#define CONFIG_NAND_MXS
> +#define CONFIG_SYS_MAX_NAND_DEVICE 1
> +#define CONFIG_SYS_NAND_BASE 0x40000000
> +#define CONFIG_SYS_NAND_5_ADDR_CYCLE
> +#define CONFIG_SYS_NAND_ONFI_DETECTION
> +
> +/* DMA stuff, needed for GPMI/MXS NAND support */
> +#define CONFIG_APBH_DMA
> +#define CONFIG_APBH_DMA_BURST
> +#define CONFIG_APBH_DMA_BURST8
> +
> +/* RTC */
> +#define CONFIG_SYS_I2C_RTC_ADDR 0x68
> +#define CONFIG_SYS_RTC_BUS_NUM 2
> +#define CONFIG_RTC_M41T11
> +#define CONFIG_CMD_DATE
> +
> +/* USB Configs */
> +#define CONFIG_CMD_USB
> +#define CONFIG_CMD_FAT
> +#define CONFIG_USB_EHCI
> +#define CONFIG_USB_EHCI_MX6
> +#define CONFIG_USB_STORAGE
> +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
> +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
> +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
> +#define CONFIG_MXC_USB_FLAGS 0
> +
> +#define ARISTAINETOS_USB_OTG_PWR IMX_GPIO_NR(4, 15)
> +#define ARISTAINETOS_USB_H1_PWR IMX_GPIO_NR(3, 31)
> +
> +/* UBI support */
> +#define CONFIG_CMD_MTDPARTS
> +#define CONFIG_MTD_PARTITIONS
> +#define CONFIG_MTD_DEVICE
> +#define CONFIG_RBTREE
> +#define CONFIG_LZO
> +#define CONFIG_CMD_UBI
> +#define CONFIG_CMD_UBIFS
> +
> +#define MTDIDS_DEFAULT "nand0=gpmi-nand"
> +#define MTDPARTS_DEFAULT "mtdparts=gpmi-nand:-(ubi)"
> +
> +#define CONFIG_MTD_UBI_FASTMAP
> +#define CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT 1
> +
> +#define CONFIG_HW_WATCHDOG
> +#define CONFIG_IMX_WATCHDOG
> +
> +#define CONFIG_FIT
> +
> +/* Framebuffer */
> +#define CONFIG_VIDEO
> +#define CONFIG_VIDEO_IPUV3
> +/* check this console not needed, after test remove it */
> +#define CONFIG_CFB_CONSOLE
> +#define CONFIG_VGA_AS_SINGLE_DEVICE
> +#define CONFIG_SYS_CONSOLE_IS_IN_ENV
> +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
> +#define CONFIG_VIDEO_BMP_RLE8
> +#define CONFIG_SPLASH_SCREEN
> +#define CONFIG_SPLASH_SCREEN_ALIGN
> +#define CONFIG_BMP_16BPP
> +#define CONFIG_VIDEO_LOGO
> +#define CONFIG_VIDEO_BMP_LOGO
> +#define CONFIG_IPUV3_CLK 198000000
> +#define CONFIG_IMX_VIDEO_SKIP
> +
> +#define CONFIG_CMD_BMP
> +
> +#endif /* __ARISTAINETOS_CONFIG_H */
>
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
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