[U-Boot] [U-boot] [Patch 3/6] ARM: keystone2: add MSMC cache coherency support for K2E SOC
Ivan Khoronzhuk
ivan.khoronzhuk at ti.com
Tue Jul 15 23:59:24 CEST 2014
From: Hao Zhang <hzhang at ti.com>
This patch adds Keystone2 K2E SOC specific code to support
MSMC cache coherency. Also create header file for msmc to hold
its API.
Acked-by: Murali Karicheri <m-karicheri2 at ti.com>
Signed-off-by: Hao Zhang <hzhang at ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk at ti.com>
---
arch/arm/cpu/armv7/keystone/init.c | 12 +++++++-----
arch/arm/cpu/armv7/keystone/msmc.c | 4 ++--
arch/arm/include/asm/arch-keystone/hardware.h | 1 -
arch/arm/include/asm/arch-keystone/msmc.h | 17 +++++++++++++++++
4 files changed, 26 insertions(+), 8 deletions(-)
create mode 100644 arch/arm/include/asm/arch-keystone/msmc.h
diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/cpu/armv7/keystone/init.c
index f4c293a..a8f8aee 100644
--- a/arch/arm/cpu/armv7/keystone/init.c
+++ b/arch/arm/cpu/armv7/keystone/init.c
@@ -10,6 +10,7 @@
#include <common.h>
#include <ns16550.h>
#include <asm/io.h>
+#include <asm/arch/msmc.h>
#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
@@ -24,11 +25,12 @@ int arch_cpu_init(void)
chip_configuration_unlock();
icache_enable();
-#ifdef CONFIG_SOC_K2HK
- share_all_segments(8);
- share_all_segments(9);
- share_all_segments(10); /* QM PDSP */
- share_all_segments(11); /* PCIE */
+ msmc_share_all_segments(8); /* TETRIS */
+ msmc_share_all_segments(9); /* NETCP */
+ msmc_share_all_segments(10); /* QM PDSP */
+ msmc_share_all_segments(11); /* PCIE 0 */
+#ifdef CONFIG_SOC_K2E
+ msmc_share_all_segments(13); /* PCIE 1 */
#endif
/*
diff --git a/arch/arm/cpu/armv7/keystone/msmc.c b/arch/arm/cpu/armv7/keystone/msmc.c
index af858fa..7d8e597 100644
--- a/arch/arm/cpu/armv7/keystone/msmc.c
+++ b/arch/arm/cpu/armv7/keystone/msmc.c
@@ -8,7 +8,7 @@
*/
#include <common.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch/msmc.h>
struct mpax {
u32 mpaxl;
@@ -56,7 +56,7 @@ struct msms_regs {
};
-void share_all_segments(int priv_id)
+void msmc_share_all_segments(int priv_id)
{
struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
int j;
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h
index 9c86b69..bcfb551 100644
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -180,7 +180,6 @@ static inline int cpu_revision(void)
return rev;
}
-void share_all_segments(int priv_id);
int cpu_to_bus(u32 *ptr, u32 length);
void sdelay(unsigned long);
diff --git a/arch/arm/include/asm/arch-keystone/msmc.h b/arch/arm/include/asm/arch-keystone/msmc.h
new file mode 100644
index 0000000..c320db5
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/msmc.h
@@ -0,0 +1,17 @@
+/*
+ * MSMC controller
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _MSMC_H_
+#define _MSMC_H_
+
+#include <asm/arch/hardware.h>
+
+void msmc_share_all_segments(int priv_id);
+
+#endif
--
1.8.3.2
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