[U-Boot] [PATCH 07/14] sunxi: dram: Use divisor P=1 for PLL5

[Ian Campbell]

On Fri, 2014-07-18 at 19:22 +0300, Siarhei Siamashka wrote:
> This configures the PLL5P clock frequency to something in the ballpark of
> 1GHz and allows more choices for MBUS and G2D clock frequency selection
> (using their own divisors). In particular, it enables the use of 2/3 clock
> speed ratio between MBUS and DRAM.
> 
> Signed-off-by: Siarhei Siamashka <siarhei.siamashka at gmail.com>

Acked-by: Ian Campbell <ijc at hellion.org.uk>