[U-Boot] [PATCH v5 05/11] exynos: dts: Adjust device tree files for U-Boot
Simon Glass
sjg at chromium.org
Tue Jul 29 19:45:55 CEST 2014
The pinctrl bindings used by Linux are an incomplete description of the
hardware. It is possible in most cases to determine the register address
of each, but not in all cases. By adding an additional property we can
fix this, and avoid adding a table to U-Boot for every single Exynos
SOC.
Signed-off-by: Simon Glass <sjg at chromium.org>
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/dts/exynos4210-pinctrl.dtsi | 1 +
arch/arm/dts/exynos4210.dtsi | 6 ++++++
arch/arm/dts/exynos4x12-pinctrl.dtsi | 6 ++++++
arch/arm/dts/exynos4x12.dtsi | 8 ++++++++
arch/arm/dts/exynos5250-pinctrl.dtsi | 4 ++++
arch/arm/dts/exynos5250.dtsi | 10 +++++++++-
arch/arm/dts/exynos5420-pinctrl.dtsi | 13 +++++++++++++
arch/arm/dts/exynos5420.dtsi | 10 ++++++++++
arch/arm/dts/exynos54xx.dtsi | 10 ++++++++++
9 files changed, 67 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/exynos4210-pinctrl.dtsi b/arch/arm/dts/exynos4210-pinctrl.dtsi
index bda17f7..d98280f 100644
--- a/arch/arm/dts/exynos4210-pinctrl.dtsi
+++ b/arch/arm/dts/exynos4210-pinctrl.dtsi
@@ -220,6 +220,7 @@
};
gpy0: gpy0 {
+ reg = <0xc00>;
gpio-controller;
#gpio-cells = <2>;
};
diff --git a/arch/arm/dts/exynos4210.dtsi b/arch/arm/dts/exynos4210.dtsi
index 48ecd7a..f521a54 100644
--- a/arch/arm/dts/exynos4210.dtsi
+++ b/arch/arm/dts/exynos4210.dtsi
@@ -82,12 +82,16 @@
};
pinctrl_0: pinctrl at 11400000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
compatible = "samsung,exynos4210-pinctrl";
reg = <0x11400000 0x1000>;
interrupts = <0 47 0>;
};
pinctrl_1: pinctrl at 11000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
compatible = "samsung,exynos4210-pinctrl";
reg = <0x11000000 0x1000>;
interrupts = <0 46 0>;
@@ -100,6 +104,8 @@
};
pinctrl_2: pinctrl at 03860000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
compatible = "samsung,exynos4210-pinctrl";
reg = <0x03860000 0x1000>;
};
diff --git a/arch/arm/dts/exynos4x12-pinctrl.dtsi b/arch/arm/dts/exynos4x12-pinctrl.dtsi
index 93f3998..3d1b0b2 100644
--- a/arch/arm/dts/exynos4x12-pinctrl.dtsi
+++ b/arch/arm/dts/exynos4x12-pinctrl.dtsi
@@ -71,6 +71,7 @@
};
gpf0: gpf0 {
+ reg = <0xc180>;
gpio-controller;
#gpio-cells = <2>;
@@ -103,6 +104,7 @@
};
gpj0: gpj0 {
+ reg = <0x240>;
gpio-controller;
#gpio-cells = <2>;
@@ -120,6 +122,7 @@
};
pinctrl at 11000000 {
+ reg = <0x40>;
gpk0: gpk0 {
gpio-controller;
#gpio-cells = <2>;
@@ -177,6 +180,7 @@
};
gpm0: gpm0 {
+ reg = <0x260>;
gpio-controller;
#gpio-cells = <2>;
@@ -217,6 +221,7 @@
};
gpy0: gpy0 {
+ reg = <0x120>;
gpio-controller;
#gpio-cells = <2>;
};
@@ -252,6 +257,7 @@
};
gpx0: gpx0 {
+ reg = <0xc00>;
gpio-controller;
#gpio-cells = <2>;
diff --git a/arch/arm/dts/exynos4x12.dtsi b/arch/arm/dts/exynos4x12.dtsi
index 5bc8f31..8d7a0c4 100644
--- a/arch/arm/dts/exynos4x12.dtsi
+++ b/arch/arm/dts/exynos4x12.dtsi
@@ -61,12 +61,16 @@
};
pinctrl_0: pinctrl at 11400000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
compatible = "samsung,exynos4x12-pinctrl";
reg = <0x11400000 0x1000>;
interrupts = <0 47 0>;
};
pinctrl_1: pinctrl at 11000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
compatible = "samsung,exynos4x12-pinctrl";
reg = <0x11000000 0x1000>;
interrupts = <0 46 0>;
@@ -79,6 +83,8 @@
};
pinctrl_2: pinctrl at 03860000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
compatible = "samsung,exynos4x12-pinctrl";
reg = <0x03860000 0x1000>;
interrupt-parent = <&combiner>;
@@ -86,6 +92,8 @@
};
pinctrl_3: pinctrl at 106E0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
compatible = "samsung,exynos4x12-pinctrl";
reg = <0x106E0000 0x1000>;
interrupts = <0 72 0>;
diff --git a/arch/arm/dts/exynos5250-pinctrl.dtsi b/arch/arm/dts/exynos5250-pinctrl.dtsi
index 67755a1..f6068e3 100644
--- a/arch/arm/dts/exynos5250-pinctrl.dtsi
+++ b/arch/arm/dts/exynos5250-pinctrl.dtsi
@@ -154,6 +154,7 @@
};
gpc4: gpc4 {
+ reg = <0x2e0>;
gpio-controller;
#gpio-cells = <2>;
@@ -162,6 +163,7 @@
};
gpx0: gpx0 {
+ reg = <0xc00>;
gpio-controller;
#gpio-cells = <2>;
@@ -293,6 +295,7 @@
};
gpv2: gpv2 {
+ reg = <0x060>;
gpio-controller;
#gpio-cells = <2>;
@@ -309,6 +312,7 @@
};
gpv4: gpv4 {
+ reg = <0xc0>;
gpio-controller;
#gpio-cells = <2>;
diff --git a/arch/arm/dts/exynos5250.dtsi b/arch/arm/dts/exynos5250.dtsi
index e22f12e..f17d288 100644
--- a/arch/arm/dts/exynos5250.dtsi
+++ b/arch/arm/dts/exynos5250.dtsi
@@ -17,6 +17,8 @@
};
pinctrl_0: pinctrl at 11400000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
compatible = "samsung,exynos5250-pinctrl";
reg = <0x11400000 0x1000>;
interrupts = <0 46 0>;
@@ -29,18 +31,24 @@
};
pinctrl_1: pinctrl at 13400000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
compatible = "samsung,exynos5250-pinctrl";
reg = <0x13400000 0x1000>;
interrupts = <0 45 0>;
};
pinctrl_2: pinctrl at 10d10000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
compatible = "samsung,exynos5250-pinctrl";
reg = <0x10d10000 0x1000>;
interrupts = <0 50 0>;
};
pinctrl_3: pinctrl at 03860000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
compatible = "samsung,exynos5250-pinctrl";
reg = <0x03860000 0x1000>;
interrupts = <0 47 0>;
@@ -49,7 +57,7 @@
i2c at 12ca0000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "samsung,s3c2440-i27c";
+ compatible = "samsung,s3c2440-i2c";
reg = <0x12CA0000 0x100>;
interrupts = <0 60 0>;
};
diff --git a/arch/arm/dts/exynos5420-pinctrl.dtsi b/arch/arm/dts/exynos5420-pinctrl.dtsi
index b3e63d1..df31f37 100644
--- a/arch/arm/dts/exynos5420-pinctrl.dtsi
+++ b/arch/arm/dts/exynos5420-pinctrl.dtsi
@@ -13,6 +13,18 @@
*/
/ {
+ /* Replicate the ordering of arch/arm/include/asm/arch-exynos/gpio.h */
+ pinctrl at 14010000 {
+ };
+ pinctrl at 13400000 {
+ };
+ pinctrl at 13410000 {
+ };
+ pinctrl at 14000000 {
+ };
+ pinctrl at 03860000 {
+ };
+
pinctrl at 13400000 {
gpy7: gpy7 {
gpio-controller;
@@ -23,6 +35,7 @@
};
gpx0: gpx0 {
+ reg = <0xc00>;
gpio-controller;
#gpio-cells = <2>;
diff --git a/arch/arm/dts/exynos5420.dtsi b/arch/arm/dts/exynos5420.dtsi
index 1087d3e..5de86d4 100644
--- a/arch/arm/dts/exynos5420.dtsi
+++ b/arch/arm/dts/exynos5420.dtsi
@@ -22,6 +22,8 @@
};
pinctrl_0: pinctrl at 13400000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
compatible = "samsung,exynos5420-pinctrl";
reg = <0x13400000 0x1000>;
interrupts = <0 45 0>;
@@ -34,24 +36,32 @@
};
pinctrl_1: pinctrl at 13410000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
compatible = "samsung,exynos5420-pinctrl";
reg = <0x13410000 0x1000>;
interrupts = <0 78 0>;
};
pinctrl_2: pinctrl at 14000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
compatible = "samsung,exynos5420-pinctrl";
reg = <0x14000000 0x1000>;
interrupts = <0 46 0>;
};
pinctrl_3: pinctrl at 14010000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
compatible = "samsung,exynos5420-pinctrl";
reg = <0x14010000 0x1000>;
interrupts = <0 50 0>;
};
pinctrl_4: pinctrl at 03860000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
compatible = "samsung,exynos5420-pinctrl";
reg = <0x03860000 0x1000>;
interrupts = <0 47 0>;
diff --git a/arch/arm/dts/exynos54xx.dtsi b/arch/arm/dts/exynos54xx.dtsi
index 1a765ab..fc0960c 100644
--- a/arch/arm/dts/exynos54xx.dtsi
+++ b/arch/arm/dts/exynos54xx.dtsi
@@ -132,6 +132,8 @@
};
pinctrl_0: pinctrl at 13400000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
compatible = "samsung,exynos5420-pinctrl";
reg = <0x13400000 0x1000>;
interrupts = <0 45 0>;
@@ -144,24 +146,32 @@
};
pinctrl_1: pinctrl at 13410000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
compatible = "samsung,exynos5420-pinctrl";
reg = <0x13410000 0x1000>;
interrupts = <0 78 0>;
};
pinctrl_2: pinctrl at 14000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
compatible = "samsung,exynos5420-pinctrl";
reg = <0x14000000 0x1000>;
interrupts = <0 46 0>;
};
pinctrl_3: pinctrl at 14010000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
compatible = "samsung,exynos5420-pinctrl";
reg = <0x14010000 0x1000>;
interrupts = <0 50 0>;
};
pinctrl_4: pinctrl at 03860000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
compatible = "samsung,exynos5420-pinctrl";
reg = <0x03860000 0x1000>;
interrupts = <0 47 0>;
--
2.0.0.526.g5318336
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