[U-Boot] [PATCH] powerpc/t4rdb: Add alternate serdes protocols to align with A-007186

Chunhe Lan Chunhe.Lan at freescale.com
Fri May 16 11:37:24 CEST 2014


A-007186: SerDes Ring VCO does not maintain lock
throughout specified temperature range.

Option 1 of the workaround states:
-------------------------------------
For all 1.25/2.5/5 GHz protocols, use LC VCO instead
of Ring VCO. Rather than selecting the SRDS_PRTCL_Sx
in the RCW, use the Alternate SRDS_PRTCL_Sx option.
The alternate option has the same functionality as
the original option; the only difference being LC VCO
rather than Ring VCO.

The alternate Protocols are:

Serdes1: 27 instead of 28
Serdes2: Not impacted
Serdes3: 1 instead of 2
Serdes4: 9 instead of 10

Signed-off-by: Chunhe Lan <Chunhe.Lan at freescale.com>
---
 board/freescale/t4rdb/eth.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c
index d220475..142c6a8 100644
--- a/board/freescale/t4rdb/eth.c
+++ b/board/freescale/t4rdb/eth.c
@@ -67,7 +67,7 @@ int board_eth_init(bd_t *bis)
 	/* Register the 10G MDIO bus */
 	fm_memac_mdio_init(bis, &tgec_mdio_info);
 
-	if (srds_prtcl_s1 == 28) {
+	if ((srds_prtcl_s1 == 28) || (srds_prtcl_s1 == 27)) {
 		/* SGMII */
 		fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1);
 		fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2);
-- 
1.7.6.5



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