[U-Boot] [PATCH v3 6/8] imx6: add data configuration file for SPL

[John Tobias]

Thanks for the info. I'll double check it again.

Regards,

john

On Sun, Nov 9, 2014 at 1:22 PM, Stefano Babic <sbabic at denx.de> wrote:
> Hi John,
>
> On 08/11/2014 22:27, John Tobias wrote:
>> This file is the default DCD configuration file for SPL
>> ---
>>  board/freescale/mx6sabresd/mx6sabresd_spl.cfg | 54 +++++++++++++++++++++++++++
>>  1 file changed, 54 insertions(+)
>>  create mode 100644 board/freescale/mx6sabresd/mx6sabresd_spl.cfg
>>
>> diff --git a/board/freescale/mx6sabresd/mx6sabresd_spl.cfg b/board/freescale/mx6sabresd/mx6sabresd_spl.cfg
>> new file mode 100644
>> index 0000000..2e2f850
>> --- /dev/null
>> +++ b/board/freescale/mx6sabresd/mx6sabresd_spl.cfg
>> @@ -0,0 +1,54 @@
>> +/*
>> + * Maintainer : Richard Hu <linuxfae at technexion.com>
>> + *
>> + * Derived from Nitrogen6x code by Boundary Devices
>> + *
>> + * SPDX-License-Identifier:  GPL-2.0+
>> + *
>> + * Refer doc/README.imximage for more details about how-to configure
>> + * and create imximage boot image
>> + *
>> + * The syntax is taken as close as possible with the kwbimage
>> + */
>> +
>
> I am expecting that this file is derived from sabresd .cfg file, not
> from something else.
>
> Not only: this file seems to me identical to novena .cfg (setup.cfg),
> copyrighted by Marek Vasut. Please carefully check copyright and
> licensing of the file you are taking and maintain the original license.
>
>> +/* image version */
>> +IMAGE_VERSION 2
>> +
>> +/*
>> + * Boot Device : one of
>> + * spi, sd (the board has no nand neither onenand)
>> + */
>> +BOOT_FROM      sd
>> +
>> +#define __ASSEMBLY__
>> +#include <config.h>
>> +#include "asm/arch/iomux.h"
>> +#include "asm/arch/crm_regs.h"
>> +
>> +/* set the default clock gate to save power */
>> +DATA 4 0x020C4068 0x00C03F3F /* CCM_CCGR0 */
>> +DATA 4 0x020C406c 0x0030FC03 /* CCM_CCGR1 */
>> +DATA 4 0x020C4070 0x0FFFC000 /* CCM_CCGR2 */
>> +DATA 4 0x020C4074 0x3FF00000 /* CCM_CCGR3 */
>> +DATA 4 0x020C4078 0xFFF300   /* CCM_CCGR4 */
>> +DATA 4 0x020C407c 0x0F0000F3 /* CCM_CCGR5 - enable SATA clocks */
>> +DATA 4 0x020C4080 0x000003FF /* CCM_CCGR6 - enable ushdc and usb clocks */
>> +
>> +/* enable AXI cache for VDOA/VPU/IPU */
>> +DATA 4 0x020e0010 0xF00000CF /* IOMUXC_GPR4 */
>> +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
>> +DATA 4 0x020e0018 0x007F007F /* IOMUXC_GPR6 */
>> +DATA 4 0x020e001c 0x007F007F /* IOMUXC_GPR7 */
>> +
>> +/*
>> + * Setup CCM_CCOSR register as follows:
>> + *
>> + * cko1_en  = 1         --> CKO1 enabled
>> + * cko1_div = 111  --> divide by 8
>> + * cko1_sel = 1011 --> ahb_clk_root
>> + *
>> + * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
>> + */
>> +DATA 4 0x020c4060 0x000000fb /* CCM_CCOSR */
>> +
>> +
>>
>
> Best regards,
> Stefano Babic
>
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