[U-Boot] [PATCH 0/1] ls1021aqds: add hwconfig setting to do pin mux

[Yuan Yao]

Added in v1: 
- Add pin mux support for ls1021aqds. 

Test log:

U-Boot 2014.07-01993-g052b512-dirty (Oct 20 2014 - 19:58:20)

CPU:   Freescale LayerScape LS1020E, Version: 1.0, (0x87081010)
Clock Configuration:
       CPU0(ARMV7):1000 MHz,
       Bus:300  MHz, DDR:800  MHz (1600 MT/s data rate),
Reset Configuration Word (RCW):
       00000000: 0608000a 00000000 00000000 00000000
       00000010: 60000000 00407900 e0025a00 21046000
       00000020: 00000000 00000000 00000000 00038000
       00000030: 00000000 001b7200 00000000 00000000
Board: LS1021AQDS
vBank: 4
Sys ID:0x2b, Sys Ver: 0x11
FPGA:  v13 (QIXIS_LS1021QDS_2014_08_27_1658), build 65386
I2C:   ready
DRAM:  Initializing DDR....using SPD
Detected UDIMM 18KSF51272AZ-1G6K1
2 GiB (DDR3, 32-bit, CL=11, ECC off)
Using SERDES1 Protocol: 96 (0x60)
Flash: 128 MiB
NAND:  0 MiB
MMC:   FSL_SDHC: 0
In:    serial
Out:   serial
Err:   serial
Net:   eTSEC1 is in sgmii mode
eTSEC2 is in sgmii mode
Phy not found
PHY reset timed out
Phy not found
PHY reset timed out
eTSEC1, eTSEC2, eTSEC3 [PRIME]
=> pri
baudrate=115200
boot=dhcp 82000000 r66431/ls1/uImage.ls1021a; tftp 8f000000 r66431/ls1/ls1021a-qds.dtb; tftp 88000000 r66431/ls1/fsl-image-x11-ls1021aqds-20140424073555.rootfs.ext2.gz.u-boot ; bootm 82000000 88000000 8f000000
boot_bank0=i2c mw 0x66 0x50 0x40;i2c mw 0x66 0x10 0x20;i2c mw 0x66 0x10 0x21
boot_bank4=i2c mw 0x66 0x50 0x44;i2c mw 0x66 0x10 0x20;i2c mw 0x66 0x10 0x21
bootargs=root=/dev/ram0 rw console=ttyS0,115200
bootdelay=3
eth1addr=00:04:9f:03:2e:c5
eth2addr=00:04:9f:03:2e:c6
eth3addr=00:04:9f:03:2e:c7
eth4addr=00:04:9f:03:2e:c8
eth5addr=00:04:9f:03:2e:c9
eth6addr=00:04:9f:03:2e:ca
ethact=eTSEC3
ethaddr=00:04:9f:03:2e:c4
ethprime=eTSEC3
fdt_high=0xffffffff
hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null,ecc=off
initrd_high=0xffffffff
ipaddr=192.168.1.121
loadaddr=0x82000000
scsidevs=0
serverip=192.168.1.1
stderr=serial
stdin=serial
stdout=serial
zhuoboot=tftp 82000000 b46552/ls1021aqds/uImage.ls1021a; tftp 8f000000 b46552/ls1021aqds/ls1021a-qds.dtb;tftp 88000000 b46552/ls1021aqds/ramdisk.small;bootm 82000000 88000000 8f000000

Environment size: 1117/8188 bytes
=> i2c md 0x66 0x5e
005e: 00 00 12 81 f7 ff ff ff ff ef e7 00 3f ff ff ff    ............?...
=> set hwconfig "fsl_ddr:ctlr_intlv=null,bank_intlv=null,ecc=off;sai"
=> save
Saving Environment to Flash...
Un-Protected 1 sectors
Erasing Flash...
. done
Erased 1 sectors
Writing to Flash... 9....8....7....6....5....4....3....2....1....9....8....7....6....5....4....3....2....1....done
Protected 1 sectors
=> run boot_bank4


U-Boot 2014.07-01993-g052b512-dirty (Oct 20 2014 - 19:58:20)

CPU:   Freescale LayerScape LS1020E, Version: 1.0, (0x87081010)
Clock Configuration:
       CPU0(ARMV7):1000 MHz,
       Bus:300  MHz, DDR:800  MHz (1600 MT/s data rate),
Reset Configuration Word (RCW):
       00000000: 0608000a 00000000 00000000 00000000
       00000010: 60000000 00407900 e0025a00 21046000
       00000020: 00000000 00000000 00000000 00038000
       00000030: 00000000 001b7200 00000000 00000000
Board: LS1021AQDS
vBank: 4
Sys ID:0x2b, Sys Ver: 0x11
FPGA:  v13 (QIXIS_LS1021QDS_2014_08_27_1658), build 65386
I2C:   ready
DRAM:  Initializing DDR....using SPD
Detected UDIMM 18KSF51272AZ-1G6K1
2 GiB (DDR3, 32-bit, CL=11, ECC off)
Using SERDES1 Protocol: 96 (0x60)
Flash: 128 MiB
NAND:  0 MiB
MMC:   FSL_SDHC: 0
In:    serial
Out:   serial
Err:   serial
Net:   eTSEC1 is in sgmii mode
eTSEC2 is in sgmii mode
Phy not found
PHY reset timed out
Phy not found
PHY reset timed out
eTSEC1, eTSEC2, eTSEC3 [PRIME]
=> i2c md 0x66 0x5e
005e: 0c 00 12 81 f7 ff ff ff ff ef e7 00 3f ff ff ff    ............?...
=>
[b46683 at rhuath ~]$