[U-Boot] [PATCH] arm: rmobile: r8a7790: Update initialize L2 cache

[Nobuhiro Iwamatsu]

Initialization of L2CTLR[5] was set only as R8A7790 by commit
237faf095fb43abbed6e40266ef7efccc8b9308b.
However, initialization of cash needs to be performed continuously.
This changes into the processing which continues initialization of
L2CTLR[5] into L2CTLR cash and performs it.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj at renesas.com>
---
 arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S | 11 ++---------
 1 file changed, 2 insertions(+), 9 deletions(-)

diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
index 879e0e0..d47546a 100644
--- a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
+++ b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
@@ -60,17 +60,10 @@ do_lowlevel_init:
 	cmp r1, #3			/* has already been set up */
 	bicne r0, r0, #0xe7
 	orrne r0, r0, #0x83		/* L2CTLR[7:6] + L2CTLR[2:0] */
-
-	ldr	r2, =0xFF000044		/* PRR */
-	ldr	r1, [r2]
-	and	r1, r1, #0x7F00
-	lsrs	r1, r1, #8
-	cmp	r1, #0x45		/* 0x45 is ID of r8a7790 */
-	bne	L2CTLR_5_SKIP
+#if defined(CONFIG_R8A7790)
 	orrne r0, r0, #0x20		/* L2CTLR[5] */
-L2CTLR_5_SKIP:
+#endif
 	mcrne p15, 1, r0, c9, c0, 2
-
 _exit_init_l2_a15:
 	ldr	r3, =(CONFIG_SYS_INIT_SP_ADDR)
 	sub	sp, r3, #4
-- 
2.1.1