On Mon, Aug 3, 2015 at 7:06 AM, Peng Fan <Peng.Fan at freescale.com> wrote: > - reg = readl(&anatop->pll_enet); > - reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT; > - reg |= freq; > + if (0 == fec_id) { Could you please use 'if (fec_id == 0)'. Same applies below.