[U-Boot] [PATCH 3/8] x86: Convert to use driver model pci on quark/galileo

[Bin Meng]

Move to driver model pci for Intel quark/galileo.

Signed-off-by: Bin Meng <bmeng.cn at gmail.com>
---

 arch/x86/cpu/quark/pci.c   | 42 ------------------------------------------
 arch/x86/cpu/quark/quark.c |  8 ++++----
 arch/x86/dts/galileo.dts   |  8 ++++++--
 configs/galileo_defconfig  |  1 +
 include/configs/galileo.h  | 12 ------------
 5 files changed, 11 insertions(+), 60 deletions(-)

diff --git a/arch/x86/cpu/quark/pci.c b/arch/x86/cpu/quark/pci.c
index a1685ad..ffef7f2 100644
--- a/arch/x86/cpu/quark/pci.c
+++ b/arch/x86/cpu/quark/pci.c
@@ -6,50 +6,8 @@
 
 #include <common.h>
 #include <pci.h>
-#include <asm/pci.h>
 #include <asm/arch/device.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
-void board_pci_setup_hose(struct pci_controller *hose)
-{
-	hose->first_busno = 0;
-	hose->last_busno = 0;
-
-	/* PCI memory space */
-	pci_set_region(hose->regions + 0,
-		       CONFIG_PCI_MEM_BUS,
-		       CONFIG_PCI_MEM_PHYS,
-		       CONFIG_PCI_MEM_SIZE,
-		       PCI_REGION_MEM);
-
-	/* PCI IO space */
-	pci_set_region(hose->regions + 1,
-		       CONFIG_PCI_IO_BUS,
-		       CONFIG_PCI_IO_PHYS,
-		       CONFIG_PCI_IO_SIZE,
-		       PCI_REGION_IO);
-
-	pci_set_region(hose->regions + 2,
-		       CONFIG_PCI_PREF_BUS,
-		       CONFIG_PCI_PREF_PHYS,
-		       CONFIG_PCI_PREF_SIZE,
-		       PCI_REGION_PREFETCH);
-
-	pci_set_region(hose->regions + 3,
-		       0,
-		       0,
-		       gd->ram_size,
-		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
-	hose->region_count = 4;
-}
-
-int board_pci_post_scan(struct pci_controller *hose)
-{
-	return 0;
-}
-
 int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
 {
 	/*
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index 12ac376..e4a7c50 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -84,7 +84,6 @@ static void quark_enable_legacy_seg(void)
 
 int arch_cpu_init(void)
 {
-	struct pci_controller *hose;
 	int ret;
 
 	post_code(POST_CPU_INIT);
@@ -96,10 +95,11 @@ int arch_cpu_init(void)
 	if (ret)
 		return ret;
 
-	ret = pci_early_init_hose(&hose);
-	if (ret)
-		return ret;
+	return 0;
+}
 
+int arch_cpu_init_dm(void)
+{
 	/*
 	 * Quark SoC has some non-standard BARs (excluding PCI standard BARs)
 	 * which need be initialized with suggested values
diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts
index d77ff8a..f119bf7 100644
--- a/arch/x86/dts/galileo.dts
+++ b/arch/x86/dts/galileo.dts
@@ -54,8 +54,11 @@
 	pci {
 		#address-cells = <3>;
 		#size-cells = <2>;
-		compatible = "intel,pci";
-		device_type = "pci";
+		compatible = "pci-x86";
+		u-boot,dm-pre-reloc;
+		ranges = <0x02000000 0x0 0x90000000 0x90000000 0 0x20000000
+			  0x42000000 0x0 0xb0000000 0xb0000000 0 0x20000000
+			  0x01000000 0x0 0x2000 0x2000 0 0xe000>;
 
 		pciuart0: uart at 14,5 {
 			compatible = "pci8086,0936.00",
@@ -63,6 +66,7 @@
 					"pciclass,070002",
 					"pciclass,0700",
 					"x86-uart";
+			u-boot,dm-pre-reloc;
 			reg = <0x0000a500 0x0 0x0 0x0 0x0
 			       0x0200a510 0x0 0x0 0x0 0x0>;
 			reg-shift = <2>;
diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig
index 6ef1090..358e87b 100644
--- a/configs/galileo_defconfig
+++ b/configs/galileo_defconfig
@@ -11,6 +11,7 @@ CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_OF_CONTROL=y
+CONFIG_DM_PCI=y
 CONFIG_SPI_FLASH=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/include/configs/galileo.h b/include/configs/galileo.h
index 3c3c6e9..b7ec279 100644
--- a/include/configs/galileo.h
+++ b/include/configs/galileo.h
@@ -20,18 +20,6 @@
 /* ns16550 UART is memory-mapped in Quark SoC */
 #undef  CONFIG_SYS_NS16550_PORT_MAPPED
 
-#define CONFIG_PCI_MEM_BUS		0x90000000
-#define CONFIG_PCI_MEM_PHYS		CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE		0x20000000
-
-#define CONFIG_PCI_PREF_BUS		0xb0000000
-#define CONFIG_PCI_PREF_PHYS		CONFIG_PCI_PREF_BUS
-#define CONFIG_PCI_PREF_SIZE		0x20000000
-
-#define CONFIG_PCI_IO_BUS		0x2000
-#define CONFIG_PCI_IO_PHYS		CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE		0xe000
-
 #define CONFIG_SYS_EARLY_PCI_INIT
 #define CONFIG_PCI_PNP
 
-- 
1.8.2.1