[U-Boot] [PATCH v2] arm/ls1021a: Add workaround for DDR erratum A008378
York Sun
yorksun at freescale.com
Mon Feb 2 15:40:34 CET 2015
On 01/31/2015 08:12 PM, Albert ARIBAUD wrote:
> Hello York Sun,
>
> On Wed, 14 Jan 2015 12:46:07 -0800, York Sun <yorksun at freescale.com>
> wrote:
>> Internal memory controller counters can reach a bad state after
>> training in DDR4 mode if accumulated ECC or DBI mode is eanbled.
>
> typo: eanbled -> enabled.
>
Thanks for catching it.
York
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