[U-Boot] [PATCH] arm: cache: always flush cache line size for page table

[Stefan Agner]

On 2016-08-02 10:55, Marek Vasut wrote:
> On 08/02/2016 07:01 PM, Stefan Agner wrote:
>> On 2016-08-02 08:56, Marek Vasut wrote:
>>> On 08/02/2016 05:47 PM, Stefan Agner wrote:
>>>> On 2016-08-02 02:38, Marek Vasut wrote:
>>>>> On 08/02/2016 09:07 AM, Stefan Agner wrote:
>>>>>> From: Stefan Agner <stefan.agner at toradex.com>
>>>>>>
>>>>>> The page table is maintained by the CPU, hence it is safe to always
>>>>>> align cache flush to a whole cache line size. This allows to use
>>>>>> mmu_page_table_flush for a single page table, e.g. when configure
>>>>>> only small regions through mmu_set_region_dcache_behaviour.
>>>>>>
>>>>>> Signed-off-by: Stefan Agner <stefan.agner at toradex.com>
>>>>>> ---
>>>>>> This avoids two messages observed on a i.MX 7 based system:
>>>>>> CACHE: Misaligned operation at range [9fff0000, 9fff0004]
>>>>>> CACHE: Misaligned operation at range [9fff0024, 9fff0028]
>>>>>>
>>>>>> Those were caused by two calls to mmu_set_region_dcache_behaviour
>>>>>> in arch/arm/imx-common/cache.c (enable_caches).
>>>>>>
>>>>>> Not sure if this is the right way to fix this... Also, we could
>>>>>> do the alignment in mmu_set_region_dcache_behaviour.
>>>>>
>>>>> This should be fixed on the driver level indeed, not in cache_v7.c
>>>>
>>>> Fixing it in enable_caches in arch/arm/imx-common/cache.c is definitely
>>>> unpractical...
>>>>
>>>> So I guess by driver level you mean in
>>>> arch/arm/lib/cache-cp15.c:mmu_set_region_dcache_behaviour
>>>> correct?
>>>>
>>>> It has the potential to code duplication in case other users of
>>>> mmu_page_table_flush need to flush page tables less than cache line
>>>> size...
>>>
>>> Isn't the function supposed to flush the whole MMU table ? Or is the
>>> idea here to really flush separate entries ?
>>
>> It has a start/stop argument, so I guess it is supposed to flush
>> separate
>> entries...
> 
> The cache ops also have start/stop argument, but they explicitly cannot
> be used on non-cache-aligned addresses, so the start/stop argument does
> not imply anything.

mmu_set_region_dcache_behaviour and mmu_page_table_flush have been added
by
Simon in one commit, and since mmu_set_region_dcache_behaviour uses it
to
flush only parts of the page table I assume it was ment to be used to
flush
(a range of) separate entries...

In the end it really depends on how we define the semantics of those two
functions... However, we need to take care of alignment in one of those
two,
it is almost impossible on the caller site of
mmu_set_region_dcache_behaviour.

Opinions?

--
Stefan