[U-Boot] [PATCH] arm: cache: always flush cache line size for page table

[Fabio Estevam]

Hi Stefan,

On Tue, Aug 2, 2016 at 4:07 AM, Stefan Agner <stefan at agner.ch> wrote:
> From: Stefan Agner <stefan.agner at toradex.com>
>
> The page table is maintained by the CPU, hence it is safe to always
> align cache flush to a whole cache line size. This allows to use
> mmu_page_table_flush for a single page table, e.g. when configure
> only small regions through mmu_set_region_dcache_behaviour.
>
> Signed-off-by: Stefan Agner <stefan.agner at toradex.com>
> ---
> This avoids two messages observed on a i.MX 7 based system:
> CACHE: Misaligned operation at range [9fff0000, 9fff0004]
> CACHE: Misaligned operation at range [9fff0024, 9fff0028]
>
> Those were caused by two calls to mmu_set_region_dcache_behaviour
> in arch/arm/imx-common/cache.c (enable_caches).
>
> Not sure if this is the right way to fix this... Also, we could
> do the alignment in mmu_set_region_dcache_behaviour.

I am also getting similar warnings on a mx6ul pico board:

U-Boot 2016.09-rc1-00245-gad6a303 (Aug 03 2016 - 10:31:52 -0300)

CPU:   Freescale i.MX6UL rev1.0 at 396 MHz
Reset cause: WDOG
Board: PICO-IMX6UL-EMMC
I2C:   ready
DRAM:  256 MiB
CACHE: Misaligned operation at range [8fff0000, 8fff0004]
CACHE: Misaligned operation at range [8fff0024, 8fff0028]
PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x11
MMC:   FSL_SDHC: 0
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Net:   FEC
Hit any key to stop autoboot:  0

Applying your patch makes these cache warnings go away.