[U-Boot] [PATCH] drivers: net: cpsw: always flush cache with cache line aligned

[Lokesh Vutla]

cpsw tries to flush dcache which is not in the range of cache line size.
Because of this the following warning comes while flushing:

CACHE: Misaligned operation at range [dffecec0, dffed016]

Fix it by flushing cache range which is cache line size aligned.

Signed-off-by: Lokesh Vutla <lokeshvutla at ti.com>
---
 drivers/net/cpsw.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c
index 2ce4ec6..631544a 100644
--- a/drivers/net/cpsw.c
+++ b/drivers/net/cpsw.c
@@ -905,9 +905,14 @@ static int _cpsw_send(struct cpsw_priv *priv, void *packet, int length)
 	void *buffer;
 	int len;
 	int timeout = CPDMA_TIMEOUT;
+	unsigned long pstart, pend;
 
-	flush_dcache_range((unsigned long)packet,
-			   (unsigned long)packet + length);
+	/*
+	 *  Make sure range is cache line aligned.
+	 */
+	pstart = (unsigned long)packet & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
+	pend = ALIGN((unsigned long)packet + length, CONFIG_SYS_CACHELINE_SIZE);
+	flush_dcache_range(pstart, pend);
 
 	/* first reap completed packets */
 	while (timeout-- &&
-- 
2.9.2