[U-Boot] [PATCH] drivers: net: cpsw: always flush cache with cache line aligned

[Joe Hershberger]

Hi Lokesh,

On Mon, Aug 8, 2016 at 1:22 AM, Lokesh Vutla <lokeshvutla at ti.com> wrote:
> cpsw tries to flush dcache which is not in the range of cache line size.
> Because of this the following warning comes while flushing:
>
> CACHE: Misaligned operation at range [dffecec0, dffed016]
>
> Fix it by flushing cache range which is cache line size aligned.

This is the send case... the transmit packet buffer from the network
subsystem is already aligned. You only need to align the size of the
packet. Also, please use PKTALIGN.

Thanks,
-Joe