[U-Boot] [PATCH] drivers: net: cpsw: always flush cache with cache line aligned

[Lokesh Vutla]

On Monday 08 August 2016 10:16 PM, Joe Hershberger wrote:
> Hi Lokesh,
> 
> On Mon, Aug 8, 2016 at 1:22 AM, Lokesh Vutla <lokeshvutla at ti.com> wrote:
>> cpsw tries to flush dcache which is not in the range of cache line size.
>> Because of this the following warning comes while flushing:
>>
>> CACHE: Misaligned operation at range [dffecec0, dffed016]
>>
>> Fix it by flushing cache range which is cache line size aligned.
> 
> This is the send case... the transmit packet buffer from the network
> subsystem is already aligned. You only need to align the size of the
> packet. Also, please use PKTALIGN.

You are right. Just posted a patch addressing your comments.

Thanks and regards,
Lokesh

> 
> Thanks,
> -Joe
>