[U-Boot] [PATCH 2/3] net: davinci_emac: Round up top buffer boundaries for dcache ops

[Karl Beldan]

check_cache_range() warns that the top boundaries are not properly
aligned while flushing and invalidating the buffers and make these
operations to fail.
ATM the RX bottom boundaries are aligned by design with EMAC_RXBUF_SIZE,
properly aligned with ARCH_DMA_MINALIGN, however the top ones are not.

This gets rid of the warnings:
CACHE: Misaligned operation at range

Signed-off-by: Karl Beldan <karl.beldan+oss at gmail.com>
---
 drivers/net/davinci_emac.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c
index 947bfab..55461b0 100644
--- a/drivers/net/davinci_emac.c
+++ b/drivers/net/davinci_emac.c
@@ -632,7 +632,8 @@ static int davinci_eth_send_packet (struct eth_device *dev,
 				      EMAC_CPPI_EOP_BIT);
 
 	flush_dcache_range((unsigned long)packet,
-			(unsigned long)packet + length);
+			   round_up((unsigned long)packet + length,
+				    ARCH_DMA_MINALIGN));
 
 	/* Send the packet */
 	writel(BD_TO_HW((unsigned long)emac_tx_desc), &adap_emac->TX0HDP);
@@ -677,7 +678,8 @@ static int davinci_eth_rcv_packet (struct eth_device *dev)
 		} else {
 			unsigned long tmp = (unsigned long)rx_curr_desc->buffer;
 
-			invalidate_dcache_range(tmp, tmp + EMAC_RXBUF_SIZE);
+			invalidate_dcache_range(tmp, round_up(tmp + EMAC_RXBUF_SIZE,
+							      ARCH_DMA_MINALIGN));
 			net_process_received_packet(
 				rx_curr_desc->buffer,
 				rx_curr_desc->buff_off_len & 0xffff);
-- 
2.9.2