[U-Boot] [PATCH] mx6ul_14x14_evk: Fix DDR calibration values

[Eric Nelson]

Hi Fabio,

On 08/29/2016 04:58 AM, Fabio Estevam wrote:
> Hi Eric,
> 
> On Mon, Aug 29, 2016 at 12:20 AM, Fabio Estevam <festevam at gmail.com> wrote:
>> From: Fabio Estevam <fabio.estevam at nxp.com>
>>
>> When running NXP 4.1 kernel with U-Boot mainline we observe a
>> hang when going into the lowest operational point of cpufreq.
>>
>> Comparing the DDR calibration values against NXP U-Boot showed
>> that the values were incorrect.
>>
>> Adjust the calibration values so that we can avoid such system hang.
>>
>> Reported-by: Eric Nelson <eric at nelint.com>
>> Signed-off-by: Fabio Estevam <fabio.estevam at nxp.com>
> 
> After running more tests I still get the hang sometimes, so we still
> need to review the DDR SPL settings.
> 
> Regards,
> 
> Fabio Estevam
> 

I just test this patch against imx/master and I'm still seeing the
issue:

	root at imx6ulevk:~#
	Bus freq set to 24000000 start...

Do you have kernel debug messages enabled so you can see the bus
frequency change?