[U-Boot] [PATCH v3 1/4] mx6: ddr: Allow changing REFSEL and REFR fields

[Eric Nelson]

Hi Fabio,

On 08/29/2016 01:35 PM, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam at nxp.com>
> 
> Currently MX6 SPL DDR initialization hardcodes the REF_SEL and
> REFR fields of the MDREF register as 1 and 7, respectively.
> 
> Looking at the MDREF initialization done via DCD we see that
> boards do need to initialize these fields differently:
> 
> $ git grep 0x021b0020 board/
> board/bachmann/ot1200/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
> board/ccv/xpress/imximage.cfg:DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */
> board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x7800
> board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x00005800
> board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
> board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
> board/freescale/mx6qsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00005800
> board/freescale/mx6qsabreauto/mx6dl.cfg:DATA 4 0x021b0020 0x00005800
> board/freescale/mx6qsabreauto/mx6qp.cfg:DATA 4 0x021b0020 0x00005800
> board/freescale/mx6sabresd/mx6dlsabresd.cfg:DATA 4      0x021b0020 0x00005800
> board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
> board/freescale/mx6slevk/imximage.cfg:DATA 4 0x021b0020 0x00001800
> board/freescale/mx6sxsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00000800
> board/freescale/mx6sxsabresd/imximage.cfg:DATA 4 0x021b0020 0x00000800
> board/warp/imximage.cfg:DATA 4 0x021b0020 0x00001800
> 
> So introduce a mechanism for users to configure REFSEL and REFR fields
> as needed.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam at nxp.com>
> ---
> Changes since v2:
> - Do not make this mx6ul specific (Eric)
> 
>  arch/arm/cpu/armv7/mx6/ddr.c            | 15 ++++++++++++---
>  arch/arm/include/asm/arch-mx6/mx6-ddr.h |  2 ++
>  2 files changed, 14 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
> index f151eec..ebc7903 100644
> --- a/arch/arm/cpu/armv7/mx6/ddr.c
> +++ b/arch/arm/cpu/armv7/mx6/ddr.c
> @@ -1183,7 +1183,7 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
>  	volatile struct mmdc_p_regs *mmdc0;
>  	volatile struct mmdc_p_regs *mmdc1;
>  	u32 val;
> -	u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
> +	u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd, refsel, refr;
>  	u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
>  	u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */
>  	u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
> @@ -1472,8 +1472,17 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
>  		MMDC1(mpzqhwctrl, val);
>  
>  	/* Step 12: Configure and activate periodic refresh */
> -	mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */
> -		       (7 << 11);  /* REFR: Refresh Rate - 8 refreshes */

Oops.

Your original patch (and what we want for the 6UL EVK) has a refsel
of zero, right?
	http://lists.denx.de/pipermail/u-boot/2016-August/265128.html

> +	if (!sysinfo->refsel)
> +		refsel = 1; /* REF_SEL: Periodic refresh cycle: 32kHz */
> +	else
> +		refsel = sysinfo->refsel;
> +
> +	if (!sysinfo->refr)
> +		refr = 7; /* REFR: Refresh Rate - 8 refreshes */
> +	else
> +		refr = sysinfo->refr;
> +
> +	mmdc0->mdref = (refsel << 14) | (refr << 11);
>