[U-Boot] [PATCH] arm64: mvebu: Fix A8K memory mapping and add documentation

[kostap at marvell.com]

From: Konstantin Porotchkin <kostap at marvell.com>

Fix the MMU mapping for A8K device family:
 - Separate CP110 master and slave memory regions
 - Fix memory regions by including IO mapping for all
   3 PCIe interfaces existing on each connected CP110 controller
This patch fixes the "Synchronous Abort" exception triggered
by RW access to PCI0 or PCI1 memory regions.
Add A8K memory mapping documentation with all regions
configured by Marvell ATF.

Signed-off-by: Konstantin Porotchkin <kostap at marvell.com>
Reviewed-by: Stefan Roese <sr at denx.de>
Cc: Stefan Roese <sr at denx.de>
Cc: Nadav Haklai <nadavh at marvell.com>
Cc: Neta Zur Hershkovits <neta at marvell.com>
Cc: Omri Itach <omrii at marvell.com>
Cc: Igal Liberman <igall at marvell.com>
Cc: Haim Boot <hayim at marvell.com>
Cc: Hanna Hawa <hannah at marvell.com>
---
 arch/arm/mach-mvebu/armada8k/cpu.c | 17 +++++++++---
 doc/mvebu/armada-8k-memory.txt     | 56 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 69 insertions(+), 4 deletions(-)
 create mode 100644 doc/mvebu/armada-8k-memory.txt

diff --git a/arch/arm/mach-mvebu/armada8k/cpu.c b/arch/arm/mach-mvebu/armada8k/cpu.c
index 2719d68..7515e45 100644
--- a/arch/arm/mach-mvebu/armada8k/cpu.c
+++ b/arch/arm/mach-mvebu/armada8k/cpu.c
@@ -21,6 +21,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define RFU_GLOBAL_SW_RST		(MVEBU_RFU_BASE + 0x84)
 #define RFU_SW_RESET_OFFSET		0
 
+/* For a detailed memory map, please see doc/mvebu/armada-8k-memory.txt */
 static struct mm_region mvebu_mem_map[] = {
 	{
 		/* RAM */
@@ -55,10 +56,18 @@ static struct mm_region mvebu_mem_map[] = {
 			 PTE_BLOCK_NON_SHARE
 	},
 	{
-		/* PCI regions */
-		.phys = 0xf8000000UL,
-		.virt = 0xf8000000UL,
-		.size = 0x08000000UL,	/* 128MiB PCI space (master & slave) */
+		/* PCI CP0 regions */
+		.phys = 0xf6000000UL,
+		.virt = 0xf6000000UL,
+		.size = 0x04000000UL,	/* 64MiB CP110 master PCI space */
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE
+	},
+	{
+		/* PCI CP1 regions */
+		.phys = 0xfa000000UL,
+		.virt = 0xfa000000UL,
+		.size = 0x04000000UL,	/* 64MiB CP110 slave PCI space */
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE
 	},
diff --git a/doc/mvebu/armada-8k-memory.txt b/doc/mvebu/armada-8k-memory.txt
new file mode 100644
index 0000000..064518e
--- /dev/null
+++ b/doc/mvebu/armada-8k-memory.txt
@@ -0,0 +1,56 @@
+		     Memory Layout on Armada-8k SoC's
+		     ================================
+
+The below desribes the physical memory layout for Marvell's Armada-8k SoC's.
+
+This assumes that the SoC includes Dual CP configuration, in case the flavor is using
+a single CP configuration, then all secondary-CP mappings are invalid.
+
+All "Reserved" areas below, are kept for future usage.
+
+Start		End			Use
+--------------------------------------------------------------------------
+0x00000000	0xEFFFFFFF		DRAM
+
+0xF0000000	0xF0FFFFFF		AP Internal registers space
+
+0xF1000000	0xF1FFFFFF		Reserved.
+
+0xF2000000	0xF3FFFFFF		CP-0 Internal (configuration) registers
+					space.
+
+0xF4000000	0xF5FFFFFF		CP-1 Internal (configuration) registers
+					space.
+
+0xF6000000	0xF6FFFFFF		CP-0 / PCIe#0 Memory space.
+
+0xF7000000	0xF7FFFFFF		CP-0 / PCIe#1 Memory space.
+
+0xF8000000	0xF8FFFFFF		CP-0 / PCIe#2 Memory space.
+
+0xF9000000	0xF900FFFF		CP-0 / PCIe#0 IO space.
+
+0xF9010000	0xF901FFFF		CP-0 / PCIe#1 IO space.
+
+0xF9020000	0xF902FFFF		CP-0 / PCIe#2 IO space.
+
+0xF9030000	0xF9FFFFFF		Reserved.
+
+0xFA000000	0xFAFFFFFF		CP-1 / PCIe#0 Memory space.
+
+0xFB000000	0xFBFFFFFF		CP-1 / PCIe#1 Memory space.
+
+0xFC000000	0xFCFFFFFF		CP-1 / PCIe#2 Memory space.
+
+0xFD000000	0xFD00FFFF		CP-1 / PCIe#0 IO space.
+
+0xFD010000	0xFD01FFFF		CP-1 / PCIe#1 IO space.
+
+0xFD020000	0xFD02FFFF		CP-1 / PCIe#2 IO space.
+
+0xFD030000	0xFFEFFFFF		Reserved.
+
+0xFFF00000	0xFFFFFFFF		Bootrom
+
+0x100000000	<DRAM Size>-1		DRAM
+
-- 
2.7.4