[U-Boot] [PATCH v4] armv7: ls102xa: Enable snooping on transactions from CAAM
Aneesh Bansal
aneesh.bansal at nxp.com
Mon Feb 8 09:34:38 CET 2016
CAAM IP lies behind SMMU in the system. Configure SMMU to do the following:
a) Program SCR to bypass transactions with stream ID other than that of CAAM
b) Program S2CR to change memroy attributes of transactions with CAAM's stream
ID (0x10) to cacheable.
CC: Alison Wang <alison.wang at nxp.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta at nxp.com>
Signed-off-by: Nitesh Narayan Lal <nitesh.lal at nxp.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal at nxp.com>
---
Changes in v4:
- Modified the Commit message
- Functionality moved to SoC Specific file
The patch is dependent on
http://patchwork.ozlabs.org/patch/579377/
arch/arm/cpu/armv7/ls102xa/soc.c | 5 +++
arch/arm/include/asm/arch-ls102xa/config.h | 2 ++
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 35 ++++++++++++++++++++
.../include/asm/arch-ls102xa/ls102xa_stream_id.h | 1 +
board/freescale/common/ls102xa_stream_id.c | 37 +++++++++++++++++++++-
5 files changed, 79 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index b1b0c71..42cd31a 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -134,5 +134,10 @@ int ls102xa_smmu_stream_id_init(void)
ls102xa_config_smmu_stream_id(dev_stream_id,
ARRAY_SIZE(dev_stream_id));
+ /* Configure SMMU to make transactions with CAAM stream ID
+ * as cacheable
+ */
+ ls1021x_config_smmu_caam_cacheable(0x10);
+
return 0;
}
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 424fe87..f189ea8 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -62,6 +62,8 @@
#define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000)
+#define SMMU_BASE (CONFIG_SYS_IMMR + 0x300000)
+
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 0a80772..61da884 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -435,4 +435,39 @@ struct ccsr_ahci {
uint get_svr(void);
+/* MMU 400 */
+#define SMMU_NSCR (SMMU_BASE + 0x400)
+#define SMMU_SMR (SMMU_BASE + 0x800)
+#define SMMU_S2CR (SMMU_BASE + 0xc00)
+
+#define SMMU_NSCR_CLIENTPD_SHIFT 0
+#define SMMU_NSCR_MTCFG_SHIFT 20
+
+#define SMR_SMR_VALID_SHIFT 31
+#define SMR_ID_MASK 0x7fff
+#define SMR_MASK_SHIFT 16
+
+#define S2CR_WACFG_SHIFT 22
+#define S2CR_WACFG_MASK 0x3
+#define S2CR_WACFG_WRITE_ALLOCATE 0x2
+
+#define S2CR_RACFG_SHIFT 20
+#define S2CR_RACFG_MASK 0x3
+#define S2CR_RACFG_READ_ALLOCATE 0x2
+
+#define S2CR_TYPE_SHIFT 16
+#define S2CR_TYPE_MASK 0x3
+#define S2CR_TYPE_BYPASS 0x01
+
+#define S2CR_MEM_ATTR_SHIFT 12
+#define S2CR_MEM_ATTR_MASK 0xf
+#define S2CR_MEM_ATTR_CACHEABLE 0xa
+
+#define S2CR_MTCFG 0x00000800
+
+#define S2CR_SHCFG_SHIFT 8
+#define S2CR_SHCFG_MASK 0x3
+#define S2CR_SHCFG_OUTER_CACHEABLE 0x1
+#define S2CR_SHCFG_INNER_CACHEABLE 0x2
+
#endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */
diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
index fa571b3..c1d22bf 100644
--- a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
+++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
@@ -71,4 +71,5 @@ struct smmu_stream_id {
void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size);
void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num);
+void ls1021x_config_smmu_caam_cacheable(uint32_t liodn);
#endif
diff --git a/board/freescale/common/ls102xa_stream_id.c b/board/freescale/common/ls102xa_stream_id.c
index f434269..8e28d64 100644
--- a/board/freescale/common/ls102xa_stream_id.c
+++ b/board/freescale/common/ls102xa_stream_id.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/ls102xa_stream_id.h>
+#include <asm/arch/immap_ls102xa.h>
void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num)
{
@@ -20,7 +21,7 @@ void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num)
void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size)
{
int i;
- u32 liodn;
+ uint32_t liodn;
for (i = 0; i < size; i++) {
if (tbl[i].num_ids == 2)
@@ -31,3 +32,37 @@ void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size)
out_le32((uint32_t *)(tbl[i].reg_offset), liodn);
}
}
+
+void ls1021x_config_smmu_caam_cacheable(uint32_t liodn)
+{
+ uint32_t *addr;
+ uint32_t smr, s2cr, nscr;
+
+ addr = (uint32_t *)(SMMU_NSCR);
+ /* SMMU NSCR configuration */
+ nscr = in_le32(addr);
+
+ nscr = nscr & ~(1 << SMMU_NSCR_CLIENTPD_SHIFT |
+ 1 << SMMU_NSCR_MTCFG_SHIFT);
+ out_le32(addr, nscr);
+
+ /* SMMU SMR configuration */
+ addr = (uint32_t *)(SMMU_SMR);
+
+ smr = 0;
+ smr = smr & (~(SMR_ID_MASK << SMR_MASK_SHIFT));
+ smr = smr | (1 << SMR_SMR_VALID_SHIFT) | liodn;
+
+ out_le32(addr, smr);
+
+ /* SMMU S2CR configuration */
+ addr = (uint32_t *)(SMMU_S2CR);
+ s2cr = (S2CR_WACFG_WRITE_ALLOCATE << S2CR_WACFG_SHIFT) |
+ (S2CR_RACFG_READ_ALLOCATE << S2CR_RACFG_SHIFT) |
+ (S2CR_TYPE_BYPASS << S2CR_TYPE_SHIFT) |
+ (S2CR_MEM_ATTR_CACHEABLE << S2CR_MEM_ATTR_SHIFT) |
+ S2CR_MTCFG |
+ (S2CR_SHCFG_OUTER_CACHEABLE << S2CR_SHCFG_SHIFT);
+
+ out_le32(addr, s2cr);
+}
--
1.8.1.4
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