[U-Boot] [PATCH] Trimslice config: update for Trimslice so SPI flash works

[Stephen Arnold]

From: Steve Arnold <stephen.arnold42 at gmail.com>

This updates the defaults for trimslice so it matches the last vendor
config.  Use the tegra-uboot-flasher tools to create mmc and spi flash
images and flash to the device. Can optionally replace boot.scr with
extlinux.conf configuration. Tested on Trimslice Diskless (with SSD).

Signed-off-by: Stephen L Arnold <nerdboy at gentoo.org>
Cc: Tom Warren <TWarren at nvidia.com>
---
Assumptions, caveats, and unknowns:
    - changes should be isolated to Trimslice
    - unknown if other Trimslice models use different values
      - only one Compulab dts u-boot release, so probably not
    - only tested on a single model, Trimslice Diskless

 include/configs/tegra-common-post.h |  2 ++
 include/configs/tegra20-common.h    |  6 ++++++
 include/configs/trimslice.h         | 14 ++++++++++++++
 3 files changed, 22 insertions(+)
---

diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h
index b206ce4..3021d8e 100644
--- a/include/configs/tegra-common-post.h
+++ b/include/configs/tegra-common-post.h
@@ -75,7 +75,9 @@
 #define BOARD_EXTRA_ENV_SETTINGS
 #endif
 
+#ifndef CONFIG_SYS_LOAD_ADDR
 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#endif
 
 #ifndef CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS
 #define CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS
diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h
index 00e85c4..b1b8819 100644
--- a/include/configs/tegra20-common.h
+++ b/include/configs/tegra20-common.h
@@ -32,7 +32,9 @@
 /*-----------------------------------------------------------------------
  * Physical Memory Map
  */
+#ifndef CONFIG_TARGET_TRIMSLICE
 #define CONFIG_SYS_TEXT_BASE	0x00110000
+#endif
 
 /*
  * Memory layout for where various images get loaded by boot scripts:
@@ -58,6 +60,7 @@
  * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
  *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
  */
+#ifndef CONFIG_TARGET_TRIMSLICE
 #define CONFIG_LOADADDR 0x01000000
 #define MEM_LAYOUT_ENV_SETTINGS \
 	"scriptaddr=0x10000000\0" \
@@ -65,6 +68,7 @@
 	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
 	"fdt_addr_r=0x02000000\0" \
 	"ramdisk_addr_r=0x02100000\0"
+#endif
 
 /* Defines for SPL */
 #define CONFIG_SPL_TEXT_BASE		0x00108000
@@ -92,7 +96,9 @@
  */
 #define CONFIG_USB_EHCI_TXFIFO_THRESH	10
 #define CONFIG_EHCI_IS_TDI
+#ifndef CONFIG_TARGET_TRIMSLICE
 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
+#endif
 
 #define CONFIG_SYS_NAND_SELF_INIT
 #define CONFIG_SYS_NAND_ONFI_DETECTION
diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h
index b761640..47149eb 100644
--- a/include/configs/trimslice.h
+++ b/include/configs/trimslice.h
@@ -14,6 +14,20 @@
 /* High-level configuration options */
 #define CONFIG_TEGRA_BOARD_STRING	"Compulab Trimslice"
 
+/* default trimslice settings (different than tegra20-common.h) */
+#define CONFIG_SYS_LOAD_ADDR   0x00A00800
+#define CONFIG_SYS_TEXT_BASE   0x0010E000
+
+#define CONFIG_LOADADDR        0x00408000
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"scriptaddr=0x10000000\0" \
+	"pxefile_addr_r=0x10100000\0" \
+	"kernel_addr_r=0x01000000\0" \
+	"fdt_addr_r=0x02000000\0" \
+	"ramdisk_addr_r=0x02100000\0"
+
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
+
 /* Board-specific serial config */
 #define CONFIG_TEGRA_ENABLE_UARTA
 #define CONFIG_TEGRA_UARTA_GPU
-- 
2.8.1