[U-Boot] [PATCH 4/7 v3] pci/layerscape: add support for LUT

[Stuart Yoder]

> -----Original Message-----
> From: york sun
> Sent: Monday, March 07, 2016 4:32 PM
> To: Stuart Yoder <stuart.yoder at nxp.com>; u-boot at lists.denx.de
> Cc: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>; Mingkai Hu <mingkai.hu at nxp.com>;
> Minghuan Lian <minghuan.lian at nxp.com>; Yang-Leo Li <leoyang.li at nxp.com>;
> marc.zyngier at arm.com
> Subject: Re: [PATCH 4/7 v3] pci/layerscape: add support for LUT
> 
> On 02/26/2016 08:52 AM, Stuart Yoder wrote:
> > From: Stuart Yoder <stuart.yoder at nxp.com>
> >
> > The per-PCI controller LUT (Look-Up-Table) is a 32-entry table
> > that maps PCI requester IDs (bus/dev/fun) to a stream ID.
> >
> > This patch implements infrastructure to enable LUT initialization:
> >   -define registers offsets
> >   -add an index to 'struct ls_pcie' to track next available slot in LUT
> >   -add function to allocate the next available entry index
> >   -add function to program a LUT entry
> >
> > Signed-off-by: Stuart Yoder <stuart.yoder at nxp.com>
> > ---
> > -v3
> >    -moved LUT #defines to immap_lsch3.h, made index
> >     allocator return an int
> >
> >  .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |    4 +++
> >  drivers/pci/pcie_layerscape.c                      |   29 ++++++++++++++++++++
> >  2 files changed, 33 insertions(+)
> >
> > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> > index 91f3ce8..d04e336 100644
> > --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> > +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> > @@ -86,6 +86,10 @@
> >  #define PCIE_LUT_BASE				0x80000
> >  #define PCIE_LUT_LCTRL0				0x7F8
> >  #define PCIE_LUT_DBG				0x7FC
> > +#define PCIE_LUT_UDR(n)         (0x800 + (n) * 8)
> > +#define PCIE_LUT_LDR(n)         (0x804 + (n) * 8)
> > +#define PCIE_LUT_ENABLE         (1 << 31)
> > +#define PCIE_LUT_ENTRY_COUNT    32
> >
> >  /* Device Configuration */
> >  #define DCFG_BASE		0x01e00000
> > diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
> > index bb29222..8b1e6fb 100644
> > --- a/drivers/pci/pcie_layerscape.c
> > +++ b/drivers/pci/pcie_layerscape.c
> > @@ -93,6 +93,7 @@ struct ls_pcie {
> >  	void __iomem *dbi;
> >  	void __iomem *va_cfg0;
> >  	void __iomem *va_cfg1;
> > +	int next_lut_index;
> >  	struct pci_controller hose;
> >  };
> >
> > @@ -482,6 +483,33 @@ static void ls_pcie_setup_ep(struct ls_pcie *pcie, struct
> ls_pcie_info *info)
> >  	}
> >  }
> >
> > +
> > +/*
> > + * Return next available LUT index.
> > + */
> > +static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
> > +{
> > +	if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
> 
> This causes compiling error on LS1043 targets. LS1043is lsch2 device. Please
> test your patch on all layerscape targets.

Yes, forgot about ls1043...will respin.

Stuart