[U-Boot] [PATCH v3 3/8] armv8: Add workaround for USB erratum A-008997
Suresh Gupta
suresh.gupta at nxp.com
Fri Feb 3 14:09:33 UTC 2017
Low Frequency Periodic Signaling (LFPS) Peak-to-Peak Differential
Output Voltage Test Compliance fails using default transmitter settings
Change settings required for transmitter signal swings to pass
compliance tests.
Signed-off-by: Sriram Dash <sriram.dash at nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat at nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta at nxp.com>
---
Changes in v2: None
Changes in V3: Change CONFIG_XXX to CONFIG_ARCH_XXX
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 +++++
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 29 ++++++++++++++++++++++
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 4 +++
.../include/asm/arch-fsl-layerscape/immap_lsch3.h | 2 ++
4 files changed, 41 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 28a0015..d5d6040 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -24,6 +24,7 @@ config ARCH_LS1043A
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
+ select SYS_FSL_ERRATUM_A008997
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_DDR4
select ARCH_EARLY_INIT_R
@@ -44,6 +45,7 @@ config ARCH_LS1046A
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
+ select SYS_FSL_ERRATUM_A008997
select SYS_FSL_HAS_DDR4
select SYS_FSL_SRDS_2
select ARCH_EARLY_INIT_R
@@ -74,6 +76,7 @@ config ARCH_LS2080A
select SYS_FSL_ERRATUM_A010165
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
+ select SYS_FSL_ERRATUM_A008997
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
@@ -161,6 +164,9 @@ config SYS_FSL_ERRATUM_A009008
config SYS_FSL_ERRATUM_A009798
bool "Workaround for USB PHY erratum A009798"
+config SYS_FSL_ERRATUM_A008997
+ bool "Workaround for USB PHY erratum A008997"
+
config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
default 4 if ARCH_LS1043A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 8d86985..c56cb72 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -94,6 +94,33 @@ static void erratum_a009798(void)
#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
}
+static void erratum_a008997(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
+#if defined(CONFIG__ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+ u32 val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB1 / 4);
+ val &= ~(0x7F << 9);
+ scfg_out32(scfg + SCFG_USB3PRM2CR_USB1 / 4,
+ val | (USB_PCSTXSWINGFULL << 9));
+ val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB2 / 4);
+ val &= ~(0x7F << 9);
+ scfg_out32(scfg + SCFG_USB3PRM2CR_USB2 / 4,
+ val | (USB_PCSTXSWINGFULL << 9));
+ val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB3 / 4);
+ val &= ~(0x7F << 9);
+ scfg_out32(scfg + SCFG_USB3PRM2CR_USB3 / 4,
+ val | (USB_PCSTXSWINGFULL << 9));
+#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS2085A)
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+ u32 val = scfg_in32(scfg + SCFG_USB3PRM2CR / 4);
+ val &= ~(0x7F << 9);
+ scfg_out32(scfg + SCFG_USB3PRM2CR / 4,
+ val | (USB_PCSTXSWINGFULL << 9));
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
+}
+
#if defined(CONFIG_FSL_LSCH3)
/*
* This erratum requires setting a value to eddrtqcr1 to
@@ -238,6 +265,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a008336();
erratum_a009008();
erratum_a009798();
+ erratum_a008997();
#ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -507,6 +535,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a010539();
erratum_a009008();
erratum_a009798();
+ erratum_a008997();
}
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 8bd40e8..2e52078 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -339,10 +339,14 @@ struct ccsr_gur {
#define SCFG_BASE 0x01570000
#define SCFG_USB3PRM1CR_USB1 0x070
+#define SCFG_USB3PRM2CR_USB1 0x074
#define SCFG_USB3PRM1CR_USB2 0x07C
+#define SCFG_USB3PRM2CR_USB2 0x080
#define SCFG_USB3PRM1CR_USB3 0x088
+#define SCFG_USB3PRM2CR_USB3 0x08c
#define USB_TXVREFTUNE 0x9
#define USB_SQRXTUNE 0xFC7FFFFF
+#define USB_PCSTXSWINGFULL 0x47
#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 3537ecb..3106ed3 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -128,9 +128,11 @@
/* Supplemental Configuration */
#define SCFG_BASE 0x01fc0000
#define SCFG_USB3PRM1CR 0x000
+#define SCFG_USB3PRM2CR 0x004
#define SCFG_USB3PRM1CR_INIT 0x27672b2a
#define USB_TXVREFTUNE 0x9
#define USB_SQRXTUNE 0xFC7FFFFF
+#define USB_PCSTXSWINGFULL 0x47
#define SCFG_QSPICLKCTLR 0x10
#define TP_ITYP_AV 0x00000001 /* Initiator available */
--
1.9.3
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