[U-Boot] cadence_qspi_apb: cache issues on mach-socfpga

[Goldschmidt Simon]

Rush, Jason A wrote;:
> I don't believe the patchset I submitted for DT bindings were merged in.

I can confirm that. I'd strongly vote for them to get in as cadence_qspi
is otherwise not usable on mach socfpga.

How can I ensure a tested-by from me gets related to that patch set?
I can't reply to it as I was not subscribed to the list at that time.

>> Regarding the bounce buffer change: isn't it wrong to use the generic bounce
>> buffer here? Given the dcache calls in it, it seems like this one is for DMA
>> but we're doing cpu copy in the cadence qspi driver.
> 
> I tend to agree for the socfpga architecture; however, I'm not very familiar with
> the bounce buffer and dcache.  From what I recall, it looked like the data is copied
> from the QSPI by the CPU on the socfpga so the data itself might be in the dcache?
> Then the call to bounce_buffer_stop invalidates the dcache, so the QSPI data that
> was there is now invalidated, and whatever random data in higher level memory
> is copied over the QSPI data.

Right. That's what my results were, too. I only discovered this after starting
this thread and sent a patch later today

Simon