[U-Boot] [U-Boot, 1/3] rockchip: rk3036: fix pll config for correct frequency

[Philipp Tomsich]

> There is a fixed div-2 between PLL and clk_ddr/clk_ddrphy,
> so we need to double to pll output and then ddr can work
> in correct frequency.
> 
> Signed-off-by: Kever Yang <kever.yang at rock-chips.com>
> ---
> 
>  arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Acked-by: Philipp Tomsich <philipp.tomsich at theobroma-systems.com>