[U-Boot] [U-Boot, 1/3] rockchip: rk3036: fix pll config for correct frequency

[Philipp Tomsich]

On Tue, 28 Nov 2017, Kever Yang wrote:

> There is a fixed div-2 between PLL and clk_ddr/clk_ddrphy,
> so we need to double to pll output and then ddr can work
> in correct frequency.
>
> Signed-off-by: Kever Yang <kever.yang at rock-chips.com>
> Acked-by: Philipp Tomsich <philipp.tomsich at theobroma-systems.com>

Reviewed-by: Philipp Tomsich <philipp.tomsich at theobroma-systems.com>

See below for requested changes.

> ---
>
> arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
> index 460dd60..51b2406 100644
> --- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
> +++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
> @@ -37,7 +37,7 @@ struct rk3036_sdram_priv {
> /* use integer mode, 396MHz dpll setting
>  * refdiv, fbdiv, postdiv1, postdiv2
>  */
> -const struct pll_div dpll_init_cfg = {1, 50, 3, 1};
> +const struct pll_div dpll_init_cfg = {1, 66, 2, 1};

This looks like the comment above should also be revised (i.e. is this 
still a setting of 396MHz?).

>
> /* 396Mhz ddr timing */
> const struct rk3036_ddr_timing ddr_timing = {0x18c,
>