[U-Boot] [PATCH] armv8: fsl-layerscape: Add back L3 flushing for all exception levels

[York Sun]

CCN-504 HPF registers were believed to be accessible only from EL3.
However, recent tests proved otherwise. Remove checking for exception
level to re-enable L3 cache flushing for all levels.

Signed-off-by: York Sun <york.sun at nxp.com>
---

 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 5ff01a0..fa93096 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -396,9 +396,6 @@ ENTRY(__asm_flush_l3_dcache)
 	mov	x29, lr
 	mov	x8, #0
 
-	switch_el x0, 1f, 100f, 100f	/* skip if not in EL3 */
-
-1:
 	dsb	sy
 	mov	x0, #0x1		/* HNFPSTAT_SFONLY */
 	bl	hnf_set_pstate
@@ -416,7 +413,6 @@ ENTRY(__asm_flush_l3_dcache)
 	bl	hnf_pstate_poll
 	cbz	x0, 1f
 	add	x8, x8, #0x2
-100:
 1:
 	mov	x0, x8
 	mov	lr, x29
-- 
2.7.4