[U-Boot] [[RESEND] PATCH v3 1/2] mmc: sdhci: add SDHCI_QUIRK_BROKEN_HISPD_MODE

[Simon Glass]

On 20 April 2018 at 02:55, Hannes Schmelzer <
hannes.schmelzer at br-automation.com> wrote:
> From: Hannes Schmelzer <oe5hpm at oevsv.at>
>
> Some IP-core implementations of the SDHCI have different troubles on the
> silicon where they are placed.
>
> On ZYNQ platform for example Xilinx doesn't accept the hold timing of an
> eMMC chip which operates in High-Speed mode and must be forced to
> operate in non high-speed mode. To get rid of this
> "SDHCI_QUIRK_BROKEN_HISPD_MODE" is introduced.
>
> For more details about this refer to the Xilinx answer-recor #59999
> https://www.xilinx.com/support/answers/59999.html
>
> This commit:
> - doesn't set HISPD bit on the host-conroller
> - reflects this fact within the host-controller capabilities
>
> Upon this the layer above (mmc-driver) can setup the card correctly.
>
> Otherwise the MMC card will be switched into high-speed mode and causes
> possible timing violation on the host-controller side.
>
> Signed-off-by: Hannes Schmelzer <oe5hpm at oevsv.at>
>
> Signed-off-by: Hannes Schmelzer <hannes.schmelzer at br-automation.com>
> ---
>
> Changes in v3:
> - cleanup sign-off tag
> - fix typo (sdci -> sdhci)
> - combine the if instruction SDHCI_QUIRK_BROKEN_HISPD_MODE with the
>   existing SDHCI_QUIRK_NO_HISPD_BIT
>
> Changes in v2:
> - don't use the SDHCI_QUIRK_NO_HISPD_BIT for getting rid of this,
> since this quirk was designed for another purpose. Instead introduce the
> new SDHCI_QUIRK_BROKEN_HISPD_MODE quirk.
>
>  drivers/mmc/sdhci.c | 8 +++++++-
>  include/sdhci.h     | 6 ++++++
>  2 files changed, 13 insertions(+), 1 deletion(-)
>

Reviewed-by: Simon Glass <sjg at chromium.org>