[U-Boot] rockchip: clk: rk3399: handle set_rate/get_rate for PLL_PPLL

[Philipp Tomsich]

> The device-tree node for the PMU clk controller assigns to its parent
> (i.e. PLL_PPLL) even though this clock currently is set up statically
> by an init-function.
> 
> In order to avoid unexpected failures, a simple implementation of
> set_rate (which accepts requests, but notifies the caller of the
> preset frequency in its return value) and get_rate (which always
> returns the preset frequency) are added.
> 
> Note that this is required for the RK808 PMIC to probe successfully on
> the RK3399-Q7, following the support for the assigned-clocks property.
> 
> References: commit f4fcba5c5baa ("clk: implement clk_set_defaults()")
> Signed-off-by: Philipp Tomsich <philipp.tomsich at theobroma-systems.com>
> Tested-by: Klaus Goger <klaus.goger at theobroma-systems.com>
> ---
> 
>  drivers/clk/rockchip/clk_rk3399.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> 2.1.4
> 

Applied to u-boot-rockchip, thanks!