[U-Boot] [PATCH v3 0/6] am335x-fb: support display PLL for lcd-clock / pixel-clock

[Hannes Schmelzer]

In most cases days ago the LCDC IP-core clock on AM335x was sourced from
the peripheral PLL with 192 MHz and the pixel clock for the connected
lcd-screen was made more or less accurate with a divider inside LCDC IP-
core.

For certain displays, example a standard VGA with 25.17 MHz pixelclock,
it is almost impossible to generate a reasonably clock with the 192 MHz
base and a simple divider. For those cases we have to use the dedicated
DPLL_DISP generating a dividable clock-source for the LCDC.

This series does this with following steps:
- adding register definition of the display PLL to clock_am33xx
- calculate mult, dividers with lowest error and setup the display PLL,
selecting as clock-source for LCDC the display PLL.
- drop the hardcoded dependency in BuR/common to the 192 MHz and
provide a real clock-frequency instead a divider
- drop the clock selection for the LCDC within board code
- do minor cosmetic cleanups (updating copyright, coding style)

Changes in v3:
- modify copyright year to 2013-2018

Changes in v2:
- am335x-fb: avoid compiler warning
- board/BuR/common: fix the !CONFIG_USE_FDT case

Hannes Schmelzer (6):
  mach-omap2: add AM335x Display PLL register definition
  am335x-fb: cosmetic: update-copyright
  am335x-fb: cosmetic: fix coding style
  am335x-fb: setup display PLL
  board/BuR: provide real clock-frequency instead a divider
  board/BuR: drop LCDC clock manipulation from board code

 arch/arm/include/asm/arch-am33xx/clock.h  |  1 +
 arch/arm/mach-omap2/am33xx/clock_am33xx.c |  7 ++++
 board/BuR/brppt1/board.c                  |  3 --
 board/BuR/brxre1/board.c                  |  2 -
 board/BuR/common/common.c                 | 14 ++-----
 drivers/video/am335x-fb.c                 | 64 +++++++++++++++++++++++++++----
 drivers/video/am335x-fb.h                 |  6 +--
 7 files changed, 71 insertions(+), 26 deletions(-)

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2.7.4